PM5362-1 Datasheet, PDF (249/354 Pages) –

PM5362 TUPP-PLUS
DATA SHEET
PMC-951010
ISSUE 6 SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR / PERFORMANCE MONITOR
Register 1F9H, 2F9H, 3F9H: RTOP, TU #4 in TUG2 #1 to TUG2 #7, PSLM
Interrupt
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
Function
Unused
PSLM7I
PSLM6I
PSLM5I
PSLM4I
PSLM3I
PSLM2I
PSLM1I
Default
X
0
0
0
0
0
0
0
This register is used to identify and acknowledge path signal label mismatch
interrupts for the tributaries TU #4 in TUG2 #1 TO TUG2 #7.
PSLM1I-PSLM7I:
The PSLM1I to PSLM7I bits identify the source of path signal label mismatch
interrupts. In TU3 mode, these bits are unused and will return a logic 0 when
read. When the corresponding TUG2 tributary group is configured for TU2
(VT6), VT3 or TU12 (VT2) mode, the associated PSLMxI bit is unused and
will return a logic 0 when read. When operational, the PSLM1I to PSLM7I bits
report and acknowledge PSLM interrupt of TU #4 in TUG2 #1 to TUG2 #7,
respectively. Interrupts are generated when the accepted PSL becomes
matched to the expected PSL or becomes mismatched to the expected PSL.
An PSLMxI bit is set high when a change of PSL matched state on the
associated tributary (TU #4 in TUG2 #x) occurs and are cleared immediately
following a read of this register, which also acknowledges and clears the
interrupt. PSLMxI remains valid when interrupts are not enabled (PSLME set
low) and may be polled to detect path signal label match/mismatch events.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 229