PL611S-17 Datasheet, PDF (5/9 Pages) PhaseLink Corporation – 1.8V-3.3V PicoPLLTM KHz to MHz Programmable Clock

P (Preliminary) L611s-17
1.8V-3.3V PicoPLL^TM KHz to MHz Programmable Clock
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
Supply Voltage Range
VDD
-0.5
7
V
Input Voltage Range
VI
-0.5
VDD+0.5
V
Output Voltage Range
VO
-0.5
VDD+0.5
V
Soldering Temperature (Green package)
260
°C
Data Retention @ 85°C
10
Year
Storage Temperature
TS
-65
150
°C
Ambient Operating Temperature*
-40
85
°C
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device
and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above
the operational limits noted in this specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to commercial grade only.
AC SPECIFICATIONS
PARAMETERS
Input (FIN) Frequency
Input (FIN) Signal Amplitude
Input (FIN) Signal Amplitude
Output Frequency
Settling Time
Output Enable Time
CONDITIONS
@ VDD =3.3V
@ VDD =2.5V
@ VDD =1.8V
Internally AC/DC coupled (High Frequency)
Internally AC/DC coupled (Low Frequency)
3.3V <50MHz, 2.5V <40MHz, 1.8V <15MHz
@ VDD =3.3V
@ VDD =2.5V
@ VDD =1.8V
At power-up (after VDD increases over 1.62V)
OE Function; Ta=25º C, 15pF Load
PDB Function; Ta=25º C, 15pF Load
Output Rise Time
Output Fall Time
15pF Load, 10/90% VDD, High Drive, 3.3V
15pF Load, 90/10% VDD, High Drive, 3.3V
Duty Cycle
VDD /2
Period Jitter, Pk-to-Pk*
With capacitive decoupling between VDD and
(measured from 10,000 samples) GND.
* Note: Jitter performance depends on the programming parameters.
MIN. TYP. MAX. UNITS
200
10KHz
166 MHz
133
0.9
VDD
Vpp
0.1
VDD
Vpp
125
90
MHz
65
2
ms
10
ns
2
ms
1.2
1.7
ns
1.2
1.7
ns
45
50
55
%
70
ps
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 01/04/07 Page 5