PL611S-17 Datasheet, PDF (1/9 Pages) PhaseLink Corporation – 1.8V-3.3V PicoPLLTM KHz to MHz Programmable Clock

P (Preliminary) L611s-17
1.8V-3.3V PicoPLL^TM KHz to MHz Programmable Clock
FEATURES
• Advanced Programmable PLL design for low-
frequency (kHz) input applications.
• Input Frequency: 10kHz to 200MHz
• OTP selectable AC/DC Input Coupling.
• Accepts >0.1V reference signal input voltage
• Very low Jitter and Phase Noise
• Output Frequency:
o <65MHz @ 1.8V operation
o <90MHz @ 2.5V operation
o <125MHz @ 3.3V operation
• Disabled outputs programmable as HiZ or Active Low.
• Offered in Tiny GREEN/RoHS compliant packages
o 6-pin DFN (2.0mmx1.3mmx0.6mm)
o 6-pin SC70 (2.3mmx2.25mmx1.0mm)
o 6-pin SOT23 (3.0mmx3.0mmx1.35mm)
• Single 1.8V, 2.5V, or 3.3V ± 10% power supply
• Operating temperature range from -40°C to 85°C
DESCRIPTION
The PL611s-17 is a low-cost general purpose
frequency synthesizer and a member of PhaseLink’s
PicoPLL^TM Factory Programmable ‘Quick Turn Clock
(QTC)’ family. Designed to fit in a small SOT23,
SC70, or DFN package for high performance, low
power applications, the PL611s-17 accepts a low
frequency (>10KHz) Reference input and generates
up to 125MHz outputs with the best phase noise,
jitter performance, and power consumption for
handheld devices and notebook applications. In
addition, one programmable I/O pin can be
configured as Output Enable (OE), Frequency
switching (FSEL), Power Down (PDB) input, or CLK1
(FOUT, FREF, FREF/2) output. Cascading the PL611s-
17 with other PicoPLL ICs can result in producing all
required system clocks with specific savings in board
space, power consumption, and cost.
PACKAGE PIN CONFIGURATION
FIN 1
OE, PDB, FSEL, CLK1 2
VDD 3
6 LF
5 GND
4 CLK0
DFN-6L
(2.0mmx1.3mmx0.6mm)
OE, PDB,
FSEL, CLK1
1
6
CLK0
VDD 2 5 GND
FIN 3 4 LF
SC70-6L
(2.3mmx2.25mmx1.0mm)
LF 1
GND 2
CLK0 3
6 FIN
5
OE, PDB,
FSEL, CLK1
4 VDD
SOT23-6L
(3.0mmx3.0mmx1.35mm)
BLOCK DIAGRAM
FIN
Ref. ^R-Counter
(7-bit)
Phase
M-Counter
Detector
(16-bit)
F_VCO = F_Ref * (M/R)
Charge
Pump
VCO
Programmable
Function
P-Counter
F_Out = F_VCO /2*P ^(4-bit)
Programming
Logic
CLK0
OE, PDB,
FSEL, CLK1
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 01/04/07 Page 1