PL611S-17 Datasheet, PDF (4/9 Pages) PhaseLink Corporation – 1.8V-3.3V PicoPLLTM KHz to MHz Programmable Clock

P (Preliminary) L611s-17
1.8V-3.3V PicoPLL^TM KHz to MHz Programmable Clock
APPLICATION RECOMMENDATIONS FOR PL611s-17
PL611s-17 can accept a reference input >10kHz and produce a clock output in the MHz range, as shown in the
diagram ‘1’, below. Also, to save costs in consumer product system designs and for greater area optimization, it
is possible to use the XOUT of the RTC crystal (32.768KHz) as the reference input to the PL611s-17, as shown in
diagram ‘2’, below.
REFIN
1
6
LF
OE, PDB
FSEL, CLK1
25
LFGND
1.8~3.3V
3
4
MHZ CLK
(Any Frequency)
XIN
C1
32.768
KHz
C2 _XOUT
XIN
ASIC
XOUT
REFIN
1
6
LF
OE, PDB
FSEL, CLK1
25
LFGND
1.8~3.3V
3
4
MHZ CLK
(Any Frequency)
Diagram ‘1’
Diagram ‘2’
Note: An AC Coupling Cap may be required if RTC Clock amplitude is too small.
GUIDELINES FOR EXTERNAL COMPONENT SELECTION
For the optimum performance, an accurate external loop filter capacitor must be selected. A general guideline for
selecting this component based on the input frequency is shown in the table below.
Input Frequency
3MHz ~ 200MHz
300KHz ~ 10MHz
30KHz ~ 1.0MHz
10KHz ~ 100KHz
Capacitor Value
1.0nF
1.0nF
4.7nF
47nF
The optimal way to choose the value is using the following formula:
C(nF) = 0.8 + M/280
Where C = Loop Filter Capacitor value (in nF)
M = M counter value. Provided by PhaseLink with device samples.
Notes:
* Find the closest commercially available value. Values in the E12 range with 5% tolerance are acceptable.
* With possible M-counter values between 1 and 65536, the capacitor value is expected in the range 820pF thru
220nF.
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 01/04/07 Page 4