PL611S-17 Datasheet, PDF (2/9 Pages) PhaseLink Corporation – 1.8V-3.3V PicoPLLTM KHz to MHz Programmable Clock

P (Preliminary) L611s-17
1.8V-3.3V PicoPLL^TM KHz to MHz Programmable Clock
KEY PROGRAMMING PARAMETERS
CLK
Output Frequency
Output Drive Strength
FOUT = FREF * (M / R) /(2*P)
Where M=16 bit
R= 7 bit
P= 4 bit
CLK0 = FOUT, FREF or FREF / (2*P)
CLK1 = FREF, FREF/2, CLK0 or CLK0/2
Three optional drive strengths to
choose from:
• Low: 4mA
• Std: 8mA (default)
• High: 16mA
Programmable
Input/Output
One output pin can be configured as:
• OE - input
• FSEL - input
• PDB - input
• CLK1 – output
• HiZ or Active Low disabled state
PACKAGE PIN ASSIGNMENT
Name
VDD
SOT
Pin#
1
Pin #
SC70
Pin#
2
DFN
Pin#
3
Type
P
Description
VDD connection.
This programmable I/O pin can be configured as Output Enable (OE)
input, Power Down (PDB) input, Frequency Selector (FSEL) or CLK1
clock output. This pin has an internal 10MΩ pull up resistor (OE, PDB &
FSEL Only).
OE, PDB,
FSEL, CLK1
2
1
The OE and PDB features can be programmed to allow the output
2
I/O _{to float (Hi Z), or to operate in the ‘Active low’ mode.}
State
OE
PDB
FSEL
0
Disable CLK Power Down Mode Frequency ‘2’
1 (default) Normal mode
Normal mode
Frequency ‘1’
FIN
LF
GND
CLK0
3
3
1
I Reference input pin.
4
4
6
I Loop Filter input pin.
5
5
5
P GND connection
6
6
4
O Programmable Clock Output
47745 Fremont Blvd., Fremont, California 94538 Tel [phone] Fax [phone] www.phaselink.com Rev 01/04/07 Page 2