PL623-38 Datasheet, PDF (4/6 Pages) PhaseLink Corporation – Low Phase Noise XO (for 3rd O.T.) For 65-130MHz

Preliminary PL623-38
Low Phase Noise XO (for 3^rd O.T.) For 65-130MHz
2. Crystal Specifications
Name
Parallel Resonant mode
Load capacitance (capacitance on
built-in on die seen by crystal)
Inter-electrode capacitance
Equivalent Series Resistance
Oscillation Frequency
Symbol
Conditions
Min.
3^rd Overtone
CL
Die only, no bond wire,
no package
C0
ESR
3^rd Overtone
65
Max.
5
4
35
130
Units
N/A
pF
pF
Ω
MHz
3. General Electrical Specifications
PARAMETERS
Supply Current (Loaded
Outputs)
Operating Voltage
Output Clock Duty Cycle
Short Circuit Current
SYMBO
L
CONDITIONS
IDD
PECL
VDD
@ Vdd – 1.3V (PECL)
MIN. TYP. MAX. UNITS
85/55
mA
2.25
3.63
V
45
50
55
%
±50
mA
4. Jitter Specifications
PARAMETERS
Period jitter RMS at 106.25MHz
Period jitter peak-to-peak at 106.25MHz
Integrated jitter RMS at 106.25MHz
*Measured on Agilent E5500.
CONDITIONS
With capacitive decoupling
between VDD and GND.
Integrated 12 kHz to 20 MHz
MIN.
TYP.
2.0
17.0
0.3*
MAX.
UNITS
ps
ps
5. Phase Noise Specifications
PARAMETERS FREQUENCY @10Hz @100Hz @1kHz
Phase Noise vs. carrier
with fund. crystal.
106.25MHz
-55
-90
-110
*: Note: Phase noise to be measured. Based on P520-20 product (fundamental 155MHz VCXO).
@10kHz @100kHz UNITS
-135
-145
dBc/Hz
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