PL623-38 Datasheet, PDF (1/6 Pages) PhaseLink Corporation – Low Phase Noise XO (for 3rd O.T.) For 65-130MHz

Preliminary PL623-38
Low Phase Noise XO (for 3^rd O.T.) For 65-130MHz
FEATURES
• Input: 65-130MHz 3^rd Overtone or fundamental
Crystal
• Output frequency: Up to 130MHz
• Selectable /2, /4, /8 output dividers with 60KΩ
pull up resistor on the selector pins
• Available output: PECL
• Supports 2.5V or 3.3V-Power Supply
• Available in die form
DESCRIPTION
PL623-38 is an XO IC specifically designed to work
with high frequency 3^rd overtone or fundamental
crystals from 65MHz to 135MHz. It requires an
external resistor for the 3^rd overtone selection. Its
design was optimized to tolerate higher limits of
inter-electrodes capacitance and bonding
capacitance to improve yield. It achieves very low
current into the crystal resulting in better overall
stability. It is ideal for XO applications requiring
PECL output levels at high frequencies.
BLOCK DIAGRAM
Oscillator
Amplifier
XIN
XOUT
OECTRL
Q
Q
PL623-38
DIE CONFIGURATION
57.5 mil
(1460,1435)
Y
X
18 17
OECTRL
19
XIN
20
16
15
14
13
12 OESEL (pull down)
11 VDDBUF
10
VDDBUF
9
Q
XOUT 21
8
Die ID: C560A-FFFF-FP
7
OECTRL 22
1
2
34
5
6
Q
GNDBUF
(0,0)
Note: ‘^’ Denotes 60kΩ pull-up resistor
DIE SPECIFICATIONS
Name
Size
Reverse side
Pad dimensions
Thickness
Value
57.5 x 56.5 mil
GND
80 micron x 80 micron
10 mil
OE SELECTION
Pad #12 Pad #22
OESEL OECTRL
State
1
0
Tri-state
1
Output enabled (default)
0
0
Output enabled (default)
(default)
1
Tri-state
Pad #12: Bond to VDD to set to “1”
Pad #22: Logical states defined by PECL levels
OUTPUT DIVIDER SELECTOR LOGIC
SEL 0
0
1
0
1
SEL1
0
0
1
1
Output
No Divider
Divide by 2
Divide by 4
Divide by 8
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