ISP1562 Datasheet, PDF (94/98 Pages) NXP Semiconductors – Hi-Speed Universal Serial Bus PCI Host Controller

Philips Semiconductors
ISP1562
USB PCI Host Controller
Interrupt Disable register bit description . . . . .43
Table 54: HcHCCA - Host Controller Communication
Area register bit allocation . . . . . . . . . . . . . . . .44
Table 55: HcHCCA - Host Controller Communication
Area register bit description . . . . . . . . . . . . . . .44
Table 56: HcPeriodCurrentED - Host Controller
Period Current Endpoint Descriptor register
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Table 57: HcPeriodCurrentED - Host Controller
Period Current Endpoint Descriptor register
bit description . . . . . . . . . . . . . . . . . . . . . . . . .45
Table 58: HcControlHeadED - Host Controller Control
Head Endpoint Descriptor register
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Table 59: HcControlHeadED - Host Controller Control
Head Endpoint Descriptor register
bit description . . . . . . . . . . . . . . . . . . . . . . . . .46
Table 60: HcControlCurrentED - Host Controller
Control Current Endpoint Descriptor register
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .46
Table 61: HcControlCurrentED - Host Controller
Control Current Endpoint Descriptor register
bit description . . . . . . . . . . . . . . . . . . . . . . . . .46
Table 62: HcBulkHeadED - Host Controller Bulk Head
Endpoint Descriptor register bit allocation . . . .47
Table 63: HcBulkHeadED - Host Controller Bulk Head
Endpoint Descriptor register bit description . . .47
Table 64: HcBulkCurrentED - Host Controller Bulk
Current Endpoint Descriptor register
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Table 65: HcBulkCurrentED - Host Controller Bulk
Current Endpoint Descriptor register
bit description . . . . . . . . . . . . . . . . . . . . . . . . .48
Table 66: HcDoneHead - Host Controller Done Head
register bit allocation . . . . . . . . . . . . . . . . . . . .48
Table 67: HcDoneHead - Host Controller Done Head
register bit description . . . . . . . . . . . . . . . . . . .49
Table 68: HcFmInterval - Host Controller Frame
Interval register bit allocation . . . . . . . . . . . . . .49
Table 69: HcFmInterval - Host Controller Frame
Interval register bit description . . . . . . . . . . . . .50
Table 70: HcFmRemaining - Host Controller Frame
Remaining register bit allocation . . . . . . . . . . .51
Table 71: HcFmRemaining - Host Controller Frame
Remaining register bit description . . . . . . . . . .51
Table 72: HcFmNumber - Host Controller Frame
Number register bit allocation . . . . . . . . . . . . .51
Table 73: HcFmNumber - Host Controller Frame
Number register bit description . . . . . . . . . . . .52
Table 74: HcPeriodicStart - Host Controller Periodic
Start register bit allocation . . . . . . . . . . . . . . . .52
Table 75: HcPeriodicStart - Host Controller Periodic
Start register bit description . . . . . . . . . . . . . . 53
Table 76: HcLSThreshold - Host Controller LS
Threshold register bit allocation . . . . . . . . . . . 53
Table 77: HcLSThreshold - Host Controller LS
Threshold register bit description . . . . . . . . . . 54
Table 78: HcRhDescriptorA - Host Controller Root
Hub Descriptor A register bit allocation . . . . . . 54
Table 79: HcRhDescriptorA - Host Controller Root
Hub Descriptor A register bit description . . . . . 55
Table 80: HcRhDescriptorB - Host Controller Root
Hub Descriptor B register bit allocation . . . . . . 56
Table 81: HcRhDescriptorB - Host Controller Root
Hub Descriptor B register bit description . . . . . 56
Table 82: HcRhStatus - Host Controller Root Hub
Status register bit allocation . . . . . . . . . . . . . . 57
Table 83: HcRhStatus - Host Controller Root Hub
Status register bit description . . . . . . . . . . . . . 57
Table 84: HcRhPortStatus[4:1] - Host Controller Root
Hub Port Status[4:1] register bit allocation . . . 58
Table 85: HcRhPortStatus[4:1] - Host Controller Root
Hub Port Status[4:1] register bit description . . 59
Table 86: CAPLENGTH/HCIVERSION - Capability
Registers Length/Host Controller Interface
Version Number register bit allocation . . . . . . . 62
Table 87: CAPLENGTH/HCIVERSION - Capability
Registers Length/Host Controller Interface
Version Number register bit description . . . . . 62
Table 88: HCSPARAMS - Host Controller Structural
Parameters register bit allocation . . . . . . . . . . 62
Table 89: HCSPARAMS - Host Controller Structural
Parameters register bit description . . . . . . . . . 63
Table 90: HCCPARAMS - Host Controller Capability
Parameters register bit allocation . . . . . . . . . . 64
Table 91: HCCPARAMS - Host Controller Capability
Parameters register bit description . . . . . . . . . 64
Table 92: USBCMD - USB Command register bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 93: USBCMD - USB Command register bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 94: USBSTS - USB Status register bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 95: USBSTS - USB Status register bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 96: USBINTR - USB Interrupt Enable
register bit allocation . . . . . . . . . . . . . . . . . . . . 70
Table 97: USBINTR - USB Interrupt Enable
register bit description . . . . . . . . . . . . . . . . . . . 70
Table 98: FRINDEX - Frame Index register bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Table 99: FRINDEX - Frame Index register bit
continued >>
9397 750 14223
Product data sheet
Rev. 01 — 14 July 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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