ISP1562 Datasheet, PDF (61/98 Pages) NXP Semiconductors – Hi-Speed Universal Serial Bus PCI Host Controller

Philips Semiconductors
ISP1562
USB PCI Host Controller
Table 85: HcRhPortStatus[4:1] - Host Controller Root Hub Port Status[4:1] register bit
description…continued
Address: Value read from func0 or func1 of address 10h + 54h
Bit
Symbol Description
2
PSS
On read—PortSuspendStatus: This bit indicates whether the port is
suspended or is in the resume sequence. It is set by a SetSuspendState
write and cleared when PSSC (PortSuspendStatusChange) is set at the
end of the resume interval. This bit is not set if CCS
(CurrentConnectStatus) is cleared. This bit is also cleared when PRSC is
set at the end of the port reset or when the Host Controller is placed in the
USBRESUME state. If an upstream resume is in progress, it will propagate
to the Host Controller.
0 — Port is not suspended
1 — Port is suspended.
On write—SetPortSuspend: The HCD can set the PSS
(PortSuspendStatus) bit by writing logic 1 to this bit. Writing logic 0 has no
effect. If CCS is cleared, this write does not set PSS; instead it sets CSS.
This informs the driver that it attempted to suspend a disconnected port.
1
PES
On read—PortEnableStatus: This bit indicates whether the port is enabled
or disabled. The Root Hub may clear this bit when an overcurrent condition,
disconnect event, switched-off power or operational bus error is detected.
This change also causes PortEnabledStatusChange to be set. The HCD
can set this bit by writing SetPortEnable and clear it by writing
ClearPortEnable. This bit cannot be set when CCS (CurrentConnectStatus)
is cleared. This bit is also set on completing a port reset when
ResetStatusChange is set or on completing a port suspend when
SuspendStatusChange is set.
0 — Port is disabled
1 — Port is enabled.
On write—SetPortEnable: The HCD can set PES (PortEnableStatus) by
writing logic 1. Writing logic 0 has no effect. If CCS is cleared, this write
does not set PES, but instead sets CSC (ConnectStatusChange). This
informs the driver that it attempted to enable a disconnected port.
0
CCS
On read—CurrentConnectStatus: This bit reflects the current state of the
downstream port.
0 — No device connected
1 — Device connected.
On write—ClearPortEnable: The HCD can write logic 1 to this bit to clear
the PES (PortEnableStatus) bit. Writing logic 0 has no effect. The CCS bit is
not affected by any write.
Remark: This bit always reads logic 1 when the attached device is
nonremovable (DeviceRemovable[NDP]).
11.2 EHCI controller capability registers
Other than the OHCI Host Controller, there are some registers in EHCI that define the
capability of EHCI. The address range of these registers is located before the operational
registers.
11.2.1 CAPLENGTH/HCIVERSION register
The bit allocation of this 4 B register is given in Table 86.
9397 750 14223
Product data sheet
Rev. 01 — 14 July 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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