ISP1562 Datasheet, PDF (58/98 Pages) NXP Semiconductors – Hi-Speed Universal Serial Bus PCI Host Controller

Philips Semiconductors
ISP1562
USB PCI Host Controller
Table 83: HcRhStatus - Host Controller Root Hub Status register bit description…continued
Address: Value read from func0 or func1 of address 10h + 50h
Bit
Symbol Description
14 to 2 reserved -
1
OCI
OverCurrentIndicator: This bit reports overcurrent conditions when global
reporting is implemented. When set, an overcurrent condition exists. When
cleared, all power operations are normal. If the per-port overcurrent
protection is implemented, this bit is always logic 0.
0
LPS
On read—LocalPowerStatus: The Root Hub does not support the local
power status feature. Therefore, this bit is always read as logic 0.
On write—ClearGlobalPower: In global power mode
(PowerSwitchingMode = 0), logic 1 is written to this bit to turn off power to
all ports (clear PortPowerStatus). In per-port power mode, it clears
PortPowerStatus only on ports whose PortPowerControlMask bit is not set.
Writing logic 0 has no effect.
11.1.22 HcRhPortStatus[4:1] register
The HcRhPortStatus[4:1] register is used to control and report port events on a per-port
basis. NumberDownstreamPorts represents the number of HcRhPortStatus registers that
are implemented in hardware. The lower word reflects the port status. The upper word
reflects the status change bits. Some status bits are implemented with special write
behavior. If a transaction—token through handshake—is in progress when a write to
change port status occurs, the resulting port status change is postponed until the
transaction completes. Always write logic 0 to the reserved bits. The bit allocation of the
register is given in Table 84.
Table 84: HcRhPortStatus[4:1] - Host Controller Root Hub Port Status[4:1] register bit allocation
Address: Value read from func0 or func1 of address 10h + 54h
Bit
31
30
29
28
27
26
25
Symbol
reserved ^[1]
Reset
0
0
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
23
22
21
20
19
18
17
Symbol
reserved ^[1]
PRSC
OCIC
PSSC
PESC
Reset
0
0
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
15
14
13
12
11
10
9
Symbol
reserved ^[1]
LSDA
Reset
0
0
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
7
6
5
4
3
2
1
Symbol
reserved ^[1]
PRS
POCI
PSS
PES
Reset
0
0
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
24
0
R/W
16
CSC
0
R/W
8
PPS
0
R/W
0
CCS
0
R/W
[1] The reserved bits should always be written with the reset value.
9397 750 14223
Product data sheet
Rev. 01 — 14 July 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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