UMA1015AM Datasheet, PDF (9/24 Pages) NXP Semiconductors – Low-power dual frequency synthesizer for radio communications

Philips Semiconductors
Low-power dual frequency synthesizer
for radio communications
Product specification
UMA1015AM
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
RF main divider input; RFA and RFB
f_RF
V_RF(rms)
Z_I
RF input frequency
RF input signal voltage
(RMS value; AC coupled)
input impedance
(real part)
50
R_s = 50 Ω;
50
f_RF = 400 to 1100 MHz
R_s = 50 Ω; f_RF = 80 to 400 MHz 150
R_s = 50 Ω; f_RF = 50 to 80 MHz 225
f_RF = 1 GHz; indicative, not
−
tested
C_I
input capacitance
indicative, not tested
−
R_pm
principle main divider ratio
512
Reference divider input; f_XTALIN
f_XTALIN
reference input frequency
3
from crystal
V_XTALIN(rms) sinusoidal input voltage
100
(RMS value)
Z_I
input impedance
(real part)
f_XTALIN = 12.8 MHz; indicative, −
not tested
C_I
input capacitance
indicative, not tested
−
R_rd
reference divider ratio
8
Charge pump current setting resistor input; I_SET
V_SET
voltage output on I_SET
R_SET = 12 to 60 kΩ
−
Charge pump outputs; CPA and CPB
I_cp
charge pump sink or
R_SET = 15 kΩ;
1.3
source current
CRA/CRB = logic 1;
I_cp = I_SET × 24;
V_cp = 0.4 V to V_CC − 0.5 V
R_SET = 15 kΩ;
0.7
CRA/CRB = logic 0;
I_cp = I_SET × 12;
V_cp = 0.4 V to V_CC − 0.5 V
I_LI
charge pump off leakage V_cp = 0.4 V to V_CC − 0.5 V
−5
current
−
−
−
−
300
1
−
−
−
10
1
−
1.1
1.75
0.9
±1
Logic input signal levels; DATA, CLK, E and HPD
V_IH
HIGH level input voltage at logic 1
V_IL
LOW level input voltage at logic 0
I_bias
input bias currents
at logic 1 or logic 0
C_I
input capacitance
indicative, not tested
0.7V_DD1 −
−0.3 −
−5
−
−
1
Port outputs/Out-of-lock; P0/OOL, P1, P2, P3 and f_XTALO - open drain outputs
V_OL
LOW level output voltage I_sink < 0.4 mA
−
−
MAX. UNIT
1 100
250
400
400
−
−
131 071
MHz
mV
mV
mV
Ω
pF
35
500
−
−
4 095
MHz
mV
kΩ
pF
−
V
2.3
mA
1.2
mA
+5
nA
V_DD1 + 0.3 V
0.3V_DD1
V
+5
µA
−
pF
0.4
V
1997 Sep 03
9