UMA1015AM Datasheet, PDF (6/24 Pages) NXP Semiconductors – Low-power dual frequency synthesizer for radio communications

Table 2 Bit allocation
FIRST
REGISTER BIT ALLOCATION
p1
p2 p3
p4 p5 p6 p7 p8 p9 p10 p11 p12 p13 p14
dt16 dt15 dt14 dt13 dt12
DATA FIELD
dt4 dt3
X
X VDON PO OLA OLB CRA CRB X
X
sPDA sPDB P3 P2
MA16
SYNTHESIZER A MAIN DIVIDER COEFFICIENT
0
00
0 SR R11
REFERENCE DIVIDER COEFFICIENT
MB16
SYNTHESIZER B MAIN DIVIDER COEFFICIENT
RESERVED FOR TEST⁽¹⁾
0
00
00 0 0 0 0
0
0
0
00
p15 p16
dt2 dt1
P1 X
sPBF 0
LAST
p17 p18 p19 p20 p21
dt0
ADDRESS
X
000
1
MA0 0 1 0
0
R0
010
1
MB0 0 1 1
0
000
0
0
100
0
Note
1. The test register should not be programmed with any other values except all zeros for normal operation.
Table 3 Bit allocation description
SYMBOL
sPDA, sPDB
sPBF
P3, P2, P1 and P0
VDON
OLA, OLB
CRA, CRB
SR
DESCRIPTION
software power-down for synthesizers A and B (0 = power-down)
software power-on for f_xtal buffer (1 = buffer on)
bits output to pins 1, 2, 9 and 19 (1 = high impedance)
voltage doubler enable (1 = doubler enabled)
out-of-lock select; selects signal output to pin 19 (see Table 4)
charge pump A/B current to I_SET ratio select (see Table 5)
reference frequency ratio select (see Table 6)
Table 4 Out-of-lock select
OLA
0
0
1
1
OLB
0
1
0
1
P0
lock status of loop B; OOLB
lock status of loop A; OOLA
logic OR function of loops A and B
OUTPUT AT PIN 19