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TDA8785 Datasheet, PDF (9/24 Pages) NXP Semiconductors – 8-bit high-speed analog-to-digital converter with gain and offset controls
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Philips Semiconductors
8-bit high-speed analog-to-digital converter
with gain and offset controls
Product specification
TDA8785
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
Slow offset amplifier inputs (pins VSOFF(p) and VSOFF(n)) gain amplifier at 0 dB; note 1
Voffset(ADC) offset voltage at ADC input
Ii
input current
VSOFF(p) = 2 V;
−
VSOFF(n) = 2.75 V
VSOFF(p) = 2.75 V;
−
VSOFF(n) = 2.75 V
VSOFF(p) = 3.5 V;
−
VSOFF(n) = 2.75 V
−
−0.25
0
0.25
10
Offset reference code; Tamb = 25 °C
OFSRE offset reference (ADC output code) Vi(p) = Vi(n);
−
8
OFSER offset reference error on code 8
VFOFF(p) = VFOFF(n);
−15
0
VSOFF(p) = VSOFF(n);
amplifier gain set at
0 dB
−
V
−
V
−
V
−
µA
−
code
+15 code
Gain control inputs (pins VFSAD(p) and VFSAD(n)); see Fig.7
Gv(min)
Gv(max)
Ii
minimum voltage gain
maximum voltage gain
input current
VFSAD(p) = 2 V;
−
−
0
dB
VFSAD(n) = 2.75 V
VFSAD(p) = 3.5 V;
20
−
VFSAD(n) = 2.75 V
−
dB
−
10
−
µA
DAC full-scale control inputs (pins VFSDAC(p) and VFSDAC(n)) 150 Ω output load on pins VDACO(p) and VDACO(n);
see Table 3
VDACO(n)
Ii
DAC negative output voltage (pin 8) code 0 at DAC inputs −
code 255 at DAC inputs; −
VFSDAC(p) = 2 V;
VFSDAC(n) = 2.75 V
code 255 at DAC inputs; −
VFSDAC(p) = 2.75 V;
VFSDAC(n) = 2.75 V
code 255 at DAC inputs; −
VFSDAC(p) = 3.5 V;
VFSDAC(n) = 2.75 V
input current
−
VCCA
−
V
VCCA − 0.4 −
V
VCCA − 0.5 −
V
VCCA − 0.6 −
V
1
−
µA
Bandwidth adjustment node input (pin B); see Fig.6
Zi
input impedance
−
500
−
Ω
8-bit DAC; fclk = 30 MHz, ramp input; Tamb = 25 °C
Zo
output impedance
INL
integral non-linearity
−
150
−
Ω
−
±0.4
±0.8 LSB
DNL
differential non-linearity
−
±0.4
±1.0 LSB
1997 Dec 18
9
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