TDA8785 Datasheet, PDF (13/24 Pages) NXP Semiconductors – 8-bit high-speed analog-to-digital converter with gain and offset controls

Philips Semiconductors
8-bit high-speed analog-to-digital converter
with gain and offset controls
Product specification
TDA8785
handbook, full pagewidth
input data
CLKDAC
t _{SU; DAT}
stable
t _{HD; DAT}
3.0 V
1.4 V
0V
MBG682
3.0 V
1.4 V
0V
The shaded areas indicate when the input data may change and be correctly registered. Data input update must be completed within 0.3 ns, after the
first rising edge of the clock (t_{SU; DAT} is negative; −0.3 ns). Data must be held at least 2 ns after the rising edge (t_{HD; DAT} = +2 ns).
Fig.3 Data set-up and hold times (DAC).
handbook, full pagewidth
CLKADC
tCPH
t _CPL
sample N
sample N + 1 sample N + 2
1.4 V
Vi(p) − Vi(n)
DATA
AD0 to AD7
t _ds
DATA
N-2
DATA
N-1
td
th
DATA
N
DATA
N+1
2.4 V
1.4 V
0.4 V
MBG683
1997 Dec 18
Fig.4 Timing diagram.
13