TDA8785 Datasheet, PDF (11/24 Pages) NXP Semiconductors – 8-bit high-speed analog-to-digital converter with gain and offset controls

Philips Semiconductors
8-bit high-speed analog-to-digital converter
with gain and offset controls
Product specification
TDA8785
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP. MAX. UNIT
Timing
ADC DIGITAL OUTPUTS (C_L = 15 pF)
t_ds
sampling delay time
t_h
output hold time
t_d
output delay time
−
1.5
−
ns
7
−
−
ns
−
−
16 ns
DAC OUTPUTS (PINS V_DACO(p) AND V_DACO(n))
t_{SU; DAT} data set-up time
note 4
−0.3
−
t_{HD; DAT} data hold time
note 4
−
−
t_S
DAC setting time (10 to 90%)
R_L = 150 Ω; C_L = 15 pF −
8
RSA
residual setting accuracy
note 5; see Fig.8
0.1
−
ns
2
ns
−
ns
2.5 %
3-STATE OUTPUT DELAY TIMES (see Fig.5)
t_dZH
enable HIGH
t_dZL
enable LOW
t_dHZ
disable HIGH
t_dLZ
disable LOW
−
15
20 ns
−
15
20 ns
−
13
20 ns
−
10
20 ns
Notes
1. V_os is proportional to the amplifier gain. For instance, V_os at 20 dB is the one indicated at 0 dB multiplied by 10.
2. It is recommended that the rise and fall times of the clock are >1 ns. In addition a good layout for the digital and
analog grounds is recommended.
3. Analog processing from signal inputs or fast offset amplifier inputs to ADC digital output; f_clk = 30 MHz; no external
filtering on pin 6 (B).
4. The data set-up time (t_{SU; DAT}) is the minimum period preceding the rising edge of the clock, that the input data must
be stable in order to be correctly registered. A negative set-up time indicates that the data may be initiated after the
rising edge and still be recognized. The data set hold time (t_{HD; DAT}) is the minimum period following the rising edge
of the clock, that the input data must be stable in order to be correctly registered. A negative hold time indicates that
the data may be released prior to the rising edge and still be recognized.
5. The residual settling accuracy is defined as follows. When a full-scale step is applied to the DAC, the initial settling
shows a fast settling behaviour. For the final part, the DAC analog output shows a slow settling behaviour.
The Residual Settling Accuracy (RSA) is defined as the full-scale error at the cross-over point at time t_X.
1997 Dec 18
11