TDA8769 Datasheet, PDF (9/28 Pages) NXP Semiconductors – 12-bit, 60/80/105 Msps Analog-to-Digital Converter (ADC) Nyquist/high IF sampling

Philips Semiconductors
12-bit, 60/80/105 Msps Analog-to-Digital Converter
(ADC) Nyquist/high IF sampling
Objective specification
TDA8769
SYMBOL PARAMETER
CONDITIONS
TEST⁽¹⁾
MIN.
TYP.
MAX. UNIT
Reference voltage input: pin VREF; note 3
V_ref(FS) full-scale fixed f_i = 25 MHz;
−
voltage
f_CLK = 105 Msps
V_i(p-p)
input voltage
V_i = V_IN − V_INN;
−
(peak-to-peak V_VREF = V_CCA3 − 1.75 V;
value)
V_i(CM) = V_CCA3 − 1.6 V
I_ref
input current
−
Full-scale voltage controlled regulator output: pin FSREF
V_o(FS)
1.9 V full-scale
−
output voltage
I_L(FS)
load current
−
Digital outputs: pins D11 to D0 and IR
V_CCA3 − 1.75 −
V
1.9
−
V
0.3
10
µA
V_CCA3 − 1.75 −
V
1
2
mA
OUTPUT LEVELS
V_OL
LOW-level
I_OL = 2 mA
output voltage
V_OH
HIGH-level
I_OH = −0.4 mA
output voltage
I_OZ
output current in output level between
3-state
0.5 V and V_CCO
TIMING; see Fig. 3
t_d(s)
sampling delay C_L = 10 pF; note 4
t_h(o)
output hold time C_L = 10 pF
t_d(o)
output delay
C_L = 10 pF
3-STATE OUTPUT DELAY
t_dZH
enable to HIGH
state
t_dZL
enable to LOW
state
t_dHZ
disable from
HIGH state
t_dLZ
disable from
LOW state
DGND
−
V_CCO − 0.5 −
−20
−
−
(tbf)
(tbf)
3.7
−
4.6
−
2.8
−
7.5
−
7.2
−
2.9
DGND + 0.5 V
V_CCO
V
+20
µA
(tbf)
ns
−
ns
(tbf)
ns
−
ns
−
ns
−
ns
−
ns
Timing complete conversion signal: pin CCS
t_d(CCS)
complete
conversion
signal delay
C_L = 10 pF; see Table 4
and Fig 4
DEL0 = LOW;
DEL1 = HIGH
DEL0 = HIGH;
DEL1 = LOW
DEL0 = HIGH;
DEL1 = HIGH
−
0
−
ns
−
1.2
−
ns
−
2.2
−
ns
2003 Dec 09
9