TDA4821P Datasheet, PDF (9/20 Pages) NXP Semiconductors – Autosize IC for colour monitors

Philips Semiconductors
Autosize IC for colour monitors
Product specification
TDA4821P
EXAMPLE OF A MEASUREMENT
On a 17-inch-screen the picture width is 320 mm. At a
horizontal frequency of 70 kHz the active video is 11 µs.
Thus, with a measuring clock of 48 MHz, there are
528 clock pulses. The start and end of the video with
respect to the leading edge of the H-sync pulse can both
be measured with an accuracy of one clock pulse. On
screen one clock pulse corresponds to ^{35----22---08--} = 0.6 mm.
An external microcontroller takes the measurements and
after calculation the new settings will be downloaded to the
deflection controller e.g. TDA4854, which has register
steps corresponding to 0.4 mm on the screen. For this
example, the positioning accuracy of the total auto-image
concept will be in the range of: 0.6 + 0.4 = 1 mm.
Since the clock is asynchronous, repeated measurements
may show jumping between two values. If the external
microcontroller takes the average of a few measurements,
the final accuracy will be improved and, as a result, the
total accuracy (measurement accuracy and register step
size) will be improved too.
OTHER SYNC PULSE CONDITIONS
The IC needs both the H-sync and V-sync pulses on
pins HS and VS respectively, for correct operation of the
capture registers.
The initial contents of the I²C-bus registers are random.
At least two V-sync pulses (one full vertical period)
together with the normal H-sync pulses are needed before
the contents become valid. Without H-sync pulses (but
with V-sync pulses) the register contents will be random.
Without V-sync pulses (but with H-sync pulses) the
register contents will be random too and the same will
happen if both H-sync and V-sync pulses are missing,
again the register contents will be random.
In the event of the application of a composite sync signal
to pin HS, the contents of the vertical capture registers
may differ slightly from the actual line count, depending on
the number of missing or additional H-sync pulses and/or
equalizing pulses during the vertical blanking time.
Table 3 Register values for missing RGB video or
horizontal flyback signals
CONDITIONS REGISTER
VALUE
No R, G or B VfstVid
video signal
maximum:
MSB = FF and LSB = F0
VlstVid
zero:
MSB = 0 and LSB = 0
HfstVid
maximum:
MSB = FF and LSB = F0
HlstVid
zero:
MSB = 0 and LSB = 0
No horizontal Hfbstrt
flyback signal
maximum:
MSB = FF and LSB = F0
Hfbstop
maximum:
MSB = FF and LSB = F0
I²C-bus interface and registers
The I²C-bus device address is 0111 010X, which means
74H for write and 75H for read.
The I²C-bus interface can handle standard I²C-bus
features, including auto-increment in the read mode, so
data byte by data byte can be read without sending a new
subaddress each time. The interface can handle both
100 and 400 kHz I²C-bus standards. Pins SDA and SCL
(5 V tolerable I/O) have digital filters, which remove all
spikes smaller than 60 ns and the threshold levels on both
pins are TTL compatible.
The contents of timing measurements, sync pulse polarity
and the clock multiplication factor are stored in
22 registers of 8-bit length (see Table 4). All read registers
are double buffered and written simultaneously on the
leading edge of the V-sync pulse. That means that the data
is stable for one complete field.
MISSING RGB VIDEO OR HORIZONTAL FLYBACK SIGNALS
If the RGB video signals or the horizontal flyback signal are
below the threshold level these signals cannot be detected
(missing signals). In that event the video and flyback
registers will have the default values (see Table 3).
2000 Feb 09
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