TDA4821P Datasheet, PDF (7/20 Pages) NXP Semiconductors – Autosize IC for colour monitors

Philips Semiconductors
Autosize IC for colour monitors
Product specification
TDA4821P
Table 1 Vertical timing measurements
TIMING
VsWidth
VfstVid
VlstVid
Vperiod
BITS
8
12
12
12
CONDITIONS
trailing edge of pulse on pin VS
first line with active video on pins VIN1, VIN2 or VIN3
last line with active video on pins VIN1, VIN2 or VIN3
next leading edge of pulse on pin VS
handbook, full pagewidth
vertical sync
(pin VS)
VsWidth
R, G, B video inputs
(pins VIN1, VIN2, VIN3)
horizontal sync
VfstVid
Vperiod
VlstVid
MHB653
Fig.3 Vertical timing.
HORIZONTAL TIMING MEASUREMENTS
The parameters are measured with respect to the leading
edge of the H-sync pulses (see Fig.4). At the leading edge
of the H-sync pulse on pin HS a 12-bit clock counter is
started (nominal internal clock frequency is 48 MHz).
The six horizontal timings (see Table 2) are countered as
a number of internal clock pulses and stored in buffer
registers. The contents of these buffer registers are copied
to the I²C-bus data registers on every next leading edge of
the V-sync pulse with the addition of LSBs (logic 0) for
completing the full 2-byte data.
The measurements of HsWidth, Hperiod, Hfbstrt and
Hfbstop in line 64 prevent wrong data capturing caused by
post-equalizing sync pulses.
The minimum horizontal frequency is 12 kHz and Hperiod
displays the full 12 bits. At 125 kHz, the shorter Hperiod
will display 9 bits only but the resolution is still better
than 0.25%.
2000 Feb 09
7