TDA4821P Datasheet, PDF (5/20 Pages) NXP Semiconductors – Autosize IC for colour monitors

Philips Semiconductors
Autosize IC for colour monitors
Product specification
TDA4821P
PINNING
SYMBOL PIN
DESCRIPTION
VIN1
1 video channel 1 input
VIN2
2 video channel 2 input
V_DD(PLL)
CLK
3 analog supply voltage of PLL
4 clock input
V_SS(I/O)
V_DD(I/O)
HS
5 ground of input/output circuit
6 supply voltage of input/output circuit
7 horizontal sync pulse input
VS
8 vertical sync pulse input
POR
9 Power-on reset input
HFB
10 horizontal flyback pulse input
TC
SCL
SDA
11 test control input
12 I²C-bus serial clock input
13 I²C-bus serial data input/output
T2
14 test mode 2 input
V_DD(core)
15 supply voltage of digital core and
comparator
V_SS(core)
CLP
16 ground of digital core
17 video clamping pulse input
T1
18 test mode 1 input
VIN3
19 video channel 3 input
LEV
20 video clamping level input
handbook, halfpage
VIN1 1
20 LEV
VIN2 2
19 VIN3
VDD(PLL) ₃
18 T1
CLK 4
17 CLP
VSS(I/O) ₅
VDD(I/O) ₆
16 ^VSS(core)
TDA4821P
15 ^VDD(core)
HS 7
14 T2
VS 8
13 SDA
POR 9
12 SCL
HFB 10
11 TC
MHB652
FUNCTIONAL DESCRIPTION
The TDA4821P consists of an RGB video comparator
input stage (see Fig.1), a clock PLL for multiplying the
external clock and a digital core which includes the
comparators for H-sync, V-sync and H-flyback pulses, the
polarity detection, the horizontal and vertical time
measurement blocks, the I²C-bus registers and interface
and the Power-on reset circuitry.
RGB video input stage
Three video input comparators are provided, suitable for
AC-coupling with capacitors of approximately 10 nF on
each input. The input pins VIN1, VIN2 and VIN3 are
suitable for the RGB video signals. The three input signals
are internally applied to an OR-circuit, so the presence of
one video signal is sufficient to activate the capture
registers.
A positive pulse is needed on pin CLP for black level
clamping. This clamping pulse must not coincide with a
possible Sync-On-Green (SOG) because SOG will not be
detected by this IC.
The black level of the video signal on pins VIN1, VIN2
and VIN3 is clamped internally to 400 mV (typical value).
This clamping level is determined by an internal divider
which is available on pin LEV and can be adjusted by an
additional external resistor divider connected to pin LEV
(see Fig.5). A small HF decoupling capacitor is needed on
pin LEV.
The video slicing level for the detection of active video is
500 mV (typical value). This level is approximately 100 mV
above the black level and is fixed by an additional internal
resistor divider from the 3.3 V supply voltage; it cannot be
modified. All signals which exceed this level are
recognized as active video. The difference between the
video slicing level and the clamping level is adjustable via
pin LEV.
Example: changing the voltage on pin LEV from
400 to 200 mV increases the threshold voltage for the
detection of active video from 100 to 300 mV.
Fig.2 Pin configuration.
2000 Feb 09
5