TDA4821P Datasheet, PDF (6/20 Pages) NXP Semiconductors – Autosize IC for colour monitors

Philips Semiconductors
Autosize IC for colour monitors
Product specification
TDA4821P
Clock PLL
In order to measure the horizontal timing with sufficient
precision, it is recommended to set the frequency of the
internal reference clock to 48 MHz. This clock is generated
by a multiplying PLL from the external clock signal applied
to pin CLK. The ratio between the internal and external
clock frequency (clock multiply factor is M_clk) is
programmable from 1 to 8 (via the I²C-bus). For instance,
for an external clock frequency of 8 MHz, a multiply factor
M_clk = 6 is needed to achieve an internal reference clock of
48 MHz.
After power-on of the IC and with an inactive I²C-bus, the
default value of factor M_clk is set to 2.
Sync and flyback pulse comparators and polarity
detection
The horizontal and vertical sync pulse input circuits on
pins HS and VS are able to handle both 5 or 3.3 V level
H/V sync pulses. The H-sync and V-sync signals are
internally preprocessed by edge detectors which deliver
positive pulses at the rising and falling edges of the input
signals and are followed by auto-polarity correction
stages. The polarity status of both sync signals will be
detected and corrected and is available as the I²C-bus
status bits Hpol and Vpol. A positive polarity means that
the duty cycle is smaller than 50% (bit Hpol = 0 or
bit Vpol = 0) and for a negative polarity the duty cycle is
larger than 50%.
The horizontal flyback pulse on pin HFB is internally
preprocessed by an edge detector in the same way as for
H-sync and V-sync pulses. The measurement of the
position of the horizontal flyback pulse provides further
information for the monitor microcontroller for a correct
auto-adjustment of the picture within the scanned raster
area.
Horizontal and vertical timing measurements
For each vertical period the IC performs six horizontal and
four vertical measurements (see Figs 3 and 4).
The leading edge of the next vertical sync pulse is used to
transfer the previous measurement results to the I²C-bus
data read registers and to reset the internal counters for
the next full timing measurement cycle. In this way the
I²C-bus data registers will always contain stable
sample-and-hold data (assuming that the sync signals are
stable) and they can be read-out via the I²C-bus by an
external microcontroller for automatic adaption of the
display geometry.
Moreover, measuring the width of the sync pulses gives
more advantages such as:
• A better mode discrimination
• In some cases the horizontal PLL of the deflection
controllers operates on the leading edge of the sync
pulse, in other cases in the middle of the sync pulse.
VERTICAL TIMING MEASUREMENTS
The parameters are measured with respect to the leading
edge of the V-sync pulse (see Fig.3). At each leading edge
of the V-sync pulse on pin VS a 12-bit counter is started.
The four vertical timings (see Table 1) are counted as a
number of H-sync pulses on pin HS and stored in buffer
registers. The contents of these buffer registers are copied
to the I²C-bus registers on every next V-sync pulse with
the addition of LSBs (logic 0) for completing the full 2-byte
data (see Table 4).
The maximum line count is 4095. With Enhanced
Graphics Adapter (EGA) systems with approximately
400 lines at 31.45 kHz, the lower line count will be 9 bits
long only but the resolution is still better than 0.25%. No
provisions are included for recognizing interlaced sync
signals with or without equal vertical periods.
2000 Feb 09
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