SA7025 Datasheet, PDF (9/22 Pages) NXP Semiconductors – Low-voltage 1GHz fractional-N synthesizer

Philips Semiconductors
1GHz low-voltage Fractional-N synthesizer
Product specification
SA7025
AC TIMING CHARACTERISTICS
DATA
D0
t_SU
CLOCK
50%
FIRST CLOCK
D1
t_H
D22,
D30
D23,
D31
D0
t_SU
LAST CLOCK
t_SU
FIRST CLOCK
STROBE
CLOCK ENABLED
SHIFT IN DATA
CLOCK
DISABLED
STORE DATA
t_W
t_SW
CLOCK
50%
STROBE (B, C, D, E) WORDS
STROBE
(A WORD)
50%
Figure 5. Serial Input Timing Sequence
SR00604
FUNCTIONAL DESCRIPTION
Serial Input Programming
The serial input is a 3-wire input (CLOCK, STROBE, DATA) to
program all counter ratios, DACs, selection and enable bits. The
programming data is structured into 24 or 32 bit words; each word
includes 1 or 4 address bits. Figure 5 shows the timing diagram of
the serial input. When the STROBE = L, the clock driver is enabled
and on the positive edges of the CLOCK the signal on DATA input is
clocked into a shift register. When the STROBE = H, the clock is
disabled and the data in the shift register remains stable.
Depending on the 1 or 4 address bits the data is latched into
different working registers or temporary registers. In order to fully
program the synthesizer, 4 words must be sent: D, C, B and A.
Figure 6 and Table 1 shows the format and the contents of each
word. The E word is for testing purposes only. The E (test) word is
reset when programming the D word. The data for CN and PR is
stored by the B word in temporary registers. When the A word is
loaded, the data of these temporary registers is loaded together with
the A word into the work registers which avoids false temporary
main divider input. CN is only loaded from the temporary registers
when a short 24 bit A0 word is used. CN will be directly loaded by
programming a long 32 bit A1 word. The flag LONG in the D word
determines whether A0 (LONG = “0”) or A1 (LONG = “1”) format is
applicable. The A word contains new data for the main divider.
Main Divider Synchronization
The A word is loaded only when a main divider synchronization
signal is also active in order to avoid phase jumps when
reprogramming the main divider. The synchronization signal is
generated by the main divider. The signal is active while the NM1
divider is counting down from the programmed value. The new A
word will be loaded after the NM1 divider has reached its terminal
count; also, at this time a main divider output pulse will be sent to
the main phase detector. The loading of the A word is disabled
while the NM2 or NM3 dividers are counting up to their programmed
values. Therefore, the new A word will be correctly loaded provided
that the STROBE signal has been at an active high value for at least
a minimum number of VCO input cycles at RF_IN or RF_IN.
t_strobe_min
+
1
f_VCO
(NM₂
@
65)
)
t_W
for PR + ‘01Ȁ
t_strobe_min
+
1
f_VCO
[NM₂ @ 65
)
(NM₃
)
1) @ 72]
)
t_W for PR + ‘10Ȁ
Programming the A word means also that the main charge pumps
on output PHP and PHI are set into the speed-up mode as long as
the STROBE is H.
Auxiliary Divider
The input signal on AUX_IN is amplified to logic level by a
single-ended CMOS input buffer, which accepts low level AC
coupled input signals. This input stage is enabled if the serial
control bit EA = “1”. Disabling means that all currents in the input
stage are switched off. A fixed divide by 4 is enabled if PA = “0”.
This divider has been optimized to accept a high frequency input
signal. If PA = “1”, this divider is disabled and the input signal is fed
directly to the second stage, which is a 12-bit programmable divider
with standard input frequency (40MHz). The division ratio can be
expressed as:
if PA = “0”: N = 4 x NA
if PA = “1”: N = NA; with NA = 4 to 4095
Reference Divider
The input signal on REF_IN is amplified to logic level by a
single-ended CMOS input buffer, which accepts low level AC
coupled input signals. This input stage is enabled by the OR
function of the serial input bits EA and EM. Disabling means that all
currents in the input stage are switched off. The reference divider
consists of a programmable divider by NR (NR = 4 to 4095) followed
by a three bit binary counter. The 2 bit SM register (see Figure 7)
determines which of the 4 output pulses is selected as the main
1996 Aug 6
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