SA7025 Datasheet, PDF (15/22 Pages) NXP Semiconductors – Low-voltage 1GHz fractional-N synthesizer

Philips Semiconductors
1GHz low-voltage Fractional-N synthesizer
Product specification
SA7025
Test Pin
The Test pin, Pin 19, is a buffered logic input which is exclusively
ORed with the output of the prescaler. The output of the XOR gate
is the input to the MAIN divider. The Test pin must be connected to
V_DD during normal operation as a synthesizer. This pin can be used
as an input for verifying the divide ratio of the MAIN divider; while in
this condition the input to the prescaler, RF_IN, may be connected to
V_CCP through a 10kΩ resistor in order to place prescaler output into
a known state.
MAIN
DIVIDER
REF
DIVIDER
SM
AUX
DIVIDER
φ_MAIN
φ_AUX
T1
T0
SELECT
LOGIC
LOCK
Figure 10. Test Mode Diagram
SR00609
PIN FUNCTIONS
PIN
No.
PIN
MNEMONIC
DC V
1 CLOCK ––
2
DATA
––
3 STROBE ––
EQUIVALENT CIRCUIT
V_DD
1
PIN
No.
PIN
MNEMONIC
DC V
9
RA
1.35
16
RN
1.35
EQUIVALENT CIRCUIT
V_DDA = 3V
9
19
TEST
––
5
RF_IN
2.1
5
6
RF_IN
2.1
8
REF_IN
1.8
10
10
AUX_IN
1.8
V_SS
V_CCP = 3V
25µA
17
RF
1.35
11
PHA
––
V_DDA
2.5k
2.5k
6
13
PHI
––
14
PHP
––
V_SS
V_DDA = 3V
V_SSA
V_DD
ENABLE
18
LOCK
––
100k
V_SS
V_SS
Figure 11. Pin Functions
V_SSA
11
18
SR00610
1996 Aug 6
15