SA7025 Datasheet, PDF(14/22 Page) NXP Semiconductors – Low-voltage 1GHz fractional-N synthesizer

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SA7025 Datasheet, PDF (14/22 Pages) NXP Semiconductors – Low-voltage 1GHz fractional-N synthesizer

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Philips Semiconductors

1GHz low-voltage Fractional-N synthesizer

Product specification

SA7025

REFERENCE R

MAIN N

VCO CYCLES

DETECTOR

OUTPUT

CONTENTS

ACCUM.

FRACTIONAL

COMPENSATION

CURRENT

N+1

TIME

PULSE-WIDTH

MODULATION

OUTPUT ON

PHP, PHI

ÂµA

PULSE-LEVEL

MODULATION

Figure 9. Waveforms for NF = 2, Fraction = 0.4

SR00608

Lock Detect

The output LOCK is H when the auxiliary phase detector AND the

main phase detector indicates a lock condition. The lock condition

is defined as a phase difference of less than +1 cycle on the

reference input REF_IN. The lock condition is also fulfilled when the

relative counter is disabled (EM = â0â or respectively EA = â0â) for

the main, respectively auxiliary counter.

Test Modes

The lock output is selectable as fREF, fAUX, fMAIN and lock. Bits T1

and T0 of the E word control the selection (see Figures 6 and 10).

If T1 = T0 = Low, or if the E-word is not sent, the lock output is

configured as the normal lock output described in the Lock Detect

section.

If T1 = Low and T0 = High, the lock output is configured as fREF.

The signal is the buffered output of the reference divider NR and the

3-bit binary counter SM. The fREF signal appears as normally low

and pulses high whenever the divider reaches terminal count from

the value programmed into the NR and SM registers. The fREF

signal can be used to verify the divide ratio of the Reference divider.

If T1 = High and T0 = Low, the lock output is configured as fAUX.

The signal is normally high and pulses low whenever the divider

reaches terminal count from the value programmed into the NA and

PA registers. The fAUX signal can be used to verify the divide ratio

of the Auxiliary divider.

If T1 = High and T0 = High, the lock output is configured as fMAIN.

The signal is the buffered output of the MAIN divider. The fMAIN

signal appears as normally high and pulses low whenever the

divider reaches terminal count from the value programmed into the

NM1, NM2 or NM3 registers. The fMAIN signal can be used to verify

the divide ratio of the MAIN divider and the prescaler.

1996 Aug 6

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