SA7025 Datasheet, PDF (6/22 Pages) NXP Semiconductors – Low-voltage 1GHz fractional-N synthesizer

Philips Semiconductors
1GHz low-voltage Fractional-N synthesizer
Product specification
SA7025
DC ELECTRICAL CHARACTERISTICS (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
Fractional compensation PHP, speed up mode ^{1, 10} V_PHP = V_DDA, V_RN = V_DDA
I_{PHP_F_S}
Fractional compensation output current
PHP vs F_RD3
I_RF = –62.5µA;F_RD = 1 to 7¹³
I_RF = –25µA;F_RD = 1 to 7
Pump leakage
Fractional compensation PHI, speed up mode ^{1, 11} V_PHP = V_DDA/2, V_RN = V_DDA
I_{PHI_F}
Fractional compensation output current
PHI vs F_RD3
I_RF = –62.5µA;F_RD = 1 to 7¹³
I_RF = –25µA;F_RD = 1 to 7
Charge pump leakage currents, charge pump not active
I_{PHP_L}
Output leakage current PHP; normal
mode¹
V_PHP = 0.7 to V_DDA – 0.8
I_{PHI_L}
Output leakage current PHI; normal
mode¹
V_PHI = 0.7 to V_DDA – 0.8
I_{PHA_L} Output leakage current PHA
V_PHA = 0.7 to V_DDA – 0.8
MIN
–3.35
–1.35
–20
–5.4
–2.15
LIMITS
TYP
–2.0
–1.0
–4.0
–1.6
UNITS
MAX
–1.1
–0.5
µA
20
nA
–2.6
µA
–1.05
0.1
10
nA
0.1
10
nA
0.1
10
nA
AC ELECTRICAL CHARACTERISTICS
V_DD = V_DDA = V_CCP = 3V; T_A = 25°C; f_{RF_IN} = 1GHz, input level = –20dBm; unless otherwise specified. Test Circuit, Figure 4. The parameters
listed below are tested using automatic test equipment to assure consistent electrical characteristics. The limits do not represent the ultimate
performance limits of the device. Use of an optimized RF layout will improve many of the listed parameters.
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
UNITS
MIN
TYP
MAX
Main divider
f_{RF_IN} Input signal frequency
Direct coupled input¹⁴
1000pF input coupling
1.04
GHz
1.04
V_{RF_IN} Input sensitivity
1040MHz
Reference divider (V_DD = V_DDA = 3V or V_DD = 3V / V_DDA = 5V)
f_{REF_IN} Input signal frequency
2.7 < V_DD and V_DDA < 5.5V
2.7 < V_DD and V_DDA < 4.5V
V_{REF_IN} Input signal range, AC coupled
2.7 < V_DD and V_DDA < 5.5V
2.7 < V_DD and V_DDA < 4.5V
Z_{REF_IN} Reference divider input impedance¹⁵
–20
500
300
100
3
0
dBm
25
MHz
30
mV_P-P
kΩ
pF
Auxiliary divider
Input signal frequency
0
50
f_{AUX_IN}
PA = “0”, prescaler enabled
Input signal frequency
4.5V ≤ V_DDA ≤ 5.5V
0
0
150
MHz
30
V_{AUX_IN}
PA = “1”, prescaler disabled
Input signal range, AC coupled
Z_{AUX_IN} Auxiliary divider input impedance
Serial interface¹⁵
4.5V ≤ V_DDA ≤ 5.5V
0
200
100
3
40
mV_P-P
kΩ
pF
f_CLOCK
t_SU
Clock frequency
Set-up time: DATA to CLOCK,
CLOCK to STROBE
10
MHz
30
ns
t_H
Hold time; CLOCK to DATA
Pulse width; CLOCK
t_W
Pulse width; STROBE
In-Loop Performance¹⁷ V_DDA = 5V, V_DD = 2.7V
R_MM
Main loop residual FM
B, C, D, E words
FVCO = 1030MHz
30
ns
30
ns
30
300
600
Hz
1996 Aug 6
6