PSMN2R0-30BL_15 Datasheet, PDF (9/15 Pages) NXP Semiconductors – N-channel 30 V 2.1 m logic level MOSFET in D2PAK

NXP Semiconductors
PSMN2R0-30BL
N-channel 30 V 2.1 mΩ logic level MOSFET in D2PAK
V_DS
I_D
V_GS(pl)
V_GS(th)
V_GS
Q_GS1 Q_GS2
Q_GS
Q_GD
Q_G(tot)
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10
V_GS
(V)
8
6
4
2
0
0
V_DS = 15V
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30
60
90
120
Q_G (nC)
Fig 13. Gate charge waveform definitions
10⁴
C
(pF)
10³
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C_iss
C_oss
C_rss
10²
10^-1
1
10
10²
V_DS (V)
Fig 14. Gate-source voltage as a function of gate
charge; typical values
100
I_S
(A)
80
60
T_j = 175 °C
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40
25 °C
20
0
0
0.5
1
1.5
2
V_SD (V)
Fig 15. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values
Fig 16. Source current as a function of source-drain
voltage; typical values
PSMN2R0-30BL
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 20 March 2012
© NXP B.V. 2012. All rights reserved.
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