74HC160 Datasheet, PDF (9/9 Pages) NXP Semiconductors – Presettable synchronous BCD decade counter; asynchronous reset

Philips Semiconductors
Presettable synchronous BCD decade
counter; asynchronous reset
Product specification
74HC/HCT160
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; t_r = t_f = 6 ns; C_L = 50 pF
T_amb (°C)
TEST CONDITIONS
SYMBOL PARAMETER
74HCT
+25
−40 to +85
−40 to +125
UNIT
V_CC
(V)
WAVEFORMS
min. typ. max. min. max. min. max.
t_PHL/ t_PLH
t_PHL
t_PLH
t_PHL
t_PHL
t_PHL
t_PLH
t_THL/ t_TLH
propagation delay
CP to Q_n
propagation delay
CP to TC
propagation delay
CP to TC
propagation delay
MR to Q_n
propagation delay
MR to TC
propagation delay
CET to TC
propagation delay
CET to TC
output transition time
25 43
54
65 ns 4.5 Fig. 8
28 48
60
72 ns 4.5 Fig. 8
23 39
49
59 ns 4.5 Fig. 8
27 50
63
75 ns 4.5 Fig. 9
30 50
63
75 ns 4.5 Fig. 9
17 35
44
53 ns 4.5 Fig. 10
9 17
21
26 ns 4.5 Fig. 10
7 15
19
22 ns 4.5 Figs 8 and 10
t_W
clock pulse width
HIGH or LOW
16 8
20
24
t_W
master reset pulse width 20 11
25
30
LOW
t_rem
removal time
MR to CP
20 9
25
30
t_su
set-up time
D_n to CP
t_su
set-up time
PE to CP
18 10
25
30
30 18
44
53
t_su
set-up time
50 30
63
75
CEP, CET to CP
t_h
hold time
D_n to CP
t_h
hold time
PE to CP
0 −8
0
0
0 −13
0
0
t_h
hold time
0 −21
0
0
CEP, CET to CP
f_max
maximum clock pulse
16 28
13
11
frequency
ns 4.5 Fig. 8
ns 4.5 Fig. 9
ns 4.5 Fig. 9
ns 4.5 Fig. 11
ns 4.5 Fig. 11
ns 4.5 Fig. 12
ns 4.5 Figs 11 and 12
ns 4.5 Figs 11 and 12
ns 4.5 Figs 11 and 12
MHz 4.5 Fig. 8
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
December 1990
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