74HC160 Datasheet, PDF (4/9 Pages) NXP Semiconductors – Presettable synchronous BCD decade counter; asynchronous reset

Philips Semiconductors
Presettable synchronous BCD decade
counter; asynchronous reset
Product specification
74HC/HCT160
Fig.4 Functional diagram.
FUNCTION TABLE
OPERATING MODE
reset (clear)
parallel load
count
hold
(do nothing)
INPUTS
OUTPUTS
MR
CP
CEP CET PE
D_n
Q_n
TC
L
X
X
X
X
X
L
L
H
↑
X
X
I
I
L
L
H
↑
X
X
I
h
H
(1)
H
↑
h
h
h
X
count
(1)
H
X
I
X
h
X
q_n
(1)
H
X
X
I
h
X
q_n
L
Notes
1. The TC output is HIGH when CET is HIGH and the counter is at terminal count (HLLH).
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition
q = lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH CP
transition
X = don’t care
↑ = LOW-to-HIGH CP transition
December 1990
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