74HC160 Datasheet, PDF (2/9 Pages) NXP Semiconductors – Presettable synchronous BCD decade counter; asynchronous reset

Philips Semiconductors
Presettable synchronous BCD decade
counter; asynchronous reset
Product specification
74HC/HCT160
FEATURES
• Synchronous counting and loading
• Two count enable inputs for n-bit cascading
• Positive-edge triggered clock
• Asynchronous reset
• Output capability: standard
• I_CC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT160 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT160 are synchronous presettable decade
counters which feature an internal look-ahead carry and
can be used for high-speed counting.
Synchronous operation is provided by having all flip-flops
clocked simultaneously on the positive-going edge of the
clock (CP).
The outputs (Q₀ to Q₃) of the counters may be preset to a
HIGH or LOW level. A LOW level at the parallel enable
input (PE) disables the counting action and causes the
data at the data inputs (D₀ to D₃) to be loaded into the
counter on the positive-going edge of the clock (providing
that the set-up and hold time requirements for PE are met).
Preset takes place regardless of the levels at count enable
inputs (CEP and CET).
A LOW level at the master reset input (MR) sets all four
outputs of the flip-flops (Q₀ to Q₃) to LOW level regardless
of the levels at CP, PE, CET and CEP inputs (thus
providing an asynchronous clear function).
The look-ahead carry simplifies serial cascading of the
counters. Both count enable inputs (CEP and CET) must
be HIGH to count. The CET input is fed forward to enable
the terminal count output (TC). The TC output thus
enabled will produce a HIGH output pulse of a duration
approximately equal to a HIGH level output of Q₀. This
pulse can be used to enable the next cascaded stage.
The maximum clock frequency for the cascaded counters
is determined by the CP to TC propagation delay and CEP
to CP set-up time, according to the following formula:
f_max = _t--P-----₍-_m-----_a--_x---₎------₍--C-----P------t--o-----T----C----1₎-----+------t--_S---_U-----(--C-----E----P-----t--o-----C----P-----)
QUICK REFERENCE DATA
GND = 0 V; T_amb= 25 °C; t_r = t_f = 6 ns
SYMBOL PARAMETER
TYPICAL
CONDITIONS
HC HCT
t_PHL
propagation delay C_L = 15 pF;
CP to Q_n
V_CC = 5 V
19
21
CP to TC
21
24
MR to Q_n
21
23
MR to TC
21
26
CET to TC
14
14
t_PLH
propagation delay
CP to Q_n
CP to TC
CET to TC
19
21
21
20
14
7
f_max
maximum clock
frequency
61
31
C_I
input capacitance
3.5
3.5
C_PD
power dissipation notes 1 and 2
capacitance per
39
34
package
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
MHz
pF
pF
Notes
1. C_PD is used to determine the
dynamic power dissipation
(P_D in µW):
P_D = C_PD × V_CC2 × f_i +
∑ (C_L × V_CC2 × f_o)
where:
f_i = input frequency in MHz
f_o = output frequency in MHz
∑ (C_L × V_CC2 × f_o) = sum of
outputs
C_L = output load capacitance in
pF
V_CC = supply voltage in V
2. For HC the condition is
V_I = GND to V_CC
For HCT the condition is
V_I = GND to V_CC − 1.5 V
December 1990
2