TDA4851 Datasheet, PDF (8/17 Pages) NXP Semiconductors – Horizontal and vertical deflection controller for VGA/XGA and autosync monitors

Philips Semiconductors
Horizontal and vertical deflection controller
for VGA/XGA and autosync monitors
Preliminary specification
TDA4851
SYMBOL
PARAMETER
Vertical sync input (DC-coupled, TTL-compatible)
V_{i sync}
sync input signal
(peak-to-peak value, pin 10)
slicing level
I₁₀
input current
t_{p V}
maximum vertical sync pulse width for
automatic vertical polarity switch
Horizontal mode detector output
V₇
output saturation voltage LOW
(for Modes 1, 2 and 3)
output voltage HIGH
I₇
load current range to force VGA
mode-dependent vertical and parabola
amplitudes
output current
VGA / autosync mode switch
V₇
input voltage LOW to force autosync
mode
Horizontal clamping / blanking generator output
V₈
output voltage LOW
blanking output voltage
clamping output voltage
I₈
internal sink current for all output levels
external load current
t₈
clamping pulse start
t_clp
clamping pulse width
S
steepness of rise and fall times
Vertical oscillator
f₀
vertical free-running frequency
f_v
nominal vertical sync range
V₁₅
voltage on pin 15
t_d
delay between sync pulse and start of
vertical scan
in VGA/XGA mode, activated by an
external resistor on pin 7
in autosync mode
I₁₂
control current for amplitude control
C₁₂
capacitor for amplitude control
CONDITIONS
V-sync on pin 10
0 < V₁₀ < 5.5 V
VGA mode
I₇ = 6 mA
mode 4
modes 1, 2 and 3
mode 4
Fig.6
internal V blanking
H-sync on pin 9
H and V scanning
V₈ = 3 V
V_ref = 6.25 V
R₁₅ = 22 kΩ;
C₁₆ = 0.1 µF
no f₀ adjustment
R₁₅ = 22 kΩ
measured on pin 8
V₇ < 50 mV
MIN. TYP. MAX. UNIT
1.7 −
1.2 1.4
−
−
−
−
−
V
1.6 V
±10 µA
300 µs
−
0.275
0.33 V
−
−
2
−
V_P
V
6
mA
−
0
0
−
−
mA
50
mV
−
−
0.9
1.6 1.9
2.2
5.15 5.4
5.65
2.3 2.9
3.5
−
−
−3.0
with end of H-sync
0.6 0.8
1.0
−
60
75
V
V
V
mA
mA
µs
ns/V
−
42
50
−
2.8 3.0
−
Hz
110 Hz
3.2 V
500 575
240 300
−
±200
−
−
650 µs
360 µs
−
µA
0.18 µF
November 1992
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