TDA4851 Datasheet, PDF (4/17 Pages) NXP Semiconductors – Horizontal and vertical deflection controller for VGA/XGA and autosync monitors

Philips Semiconductors
Horizontal and vertical deflection controller
for VGA/XGA and autosync monitors
Preliminary specification
TDA4851
PINNING
SYMBOL
V_P
FLB
HOR
GND
VERT1
VERT2
MODE
CLBL
HVS
VS
EW
C_VA
R_VA
R_EW
R_VOS
C_VOS
PLL1
R_HOS
C_HOS
PLL2
PIN
DESCRIPTION
1 positive supply voltage
2 horizontal flyback input
3 horizontal output
4 ground (0 V)
5 vertical output 1; negative-going sawtooth
6 vertical output 2; positive-going sawtooth
7 4th mode output and autosync input
8 clamping/blanking pulse output
9 horizontal sync/video input
10 vertical sync input
11 E/W output (parabola to driver stage)
12 capacitor for amplitude control
13 vertical amplitude adjustment input
14 E/W amplitude adjustment input (parabola)
15 vertical oscillator resistor
16 vertical oscillator capacitor
17 PLL1 phase
18 horizontal oscillator resistor
19 horizontal oscillator capacitor
20 PLL2 phase
Fig.2 Pin configuration.
FUNCTIONAL DESCRIPTION
Horizontal sync separator and polarity correction
An AC-coupled video signal or a DC-coupled TTL sync
signal (H only or composite sync) is input on pin 9. Video
signals are clamped with top sync on 1.28 V, and are
sliced at 1.4 V. This results in a fixed absolute slicing level
of 120 mV related to top sync.
DC-coupled TTL sync signals are also sliced at 1.4 V,
however with the clamping circuit in current limitation.
The polarity of the separated sync is detected by internal
integration of the signal, then the polarity is corrected.
The polarity information is fed to the VGA mode detector.
The corrected sync is input signal for the vertical sync
integrator and the PLL1 stage.
Vertical sync separator, polarity correction and
vertical sync integrator
DC-coupled vertical TTL sync signals may be applied to
pin 10. They are sliced at 1.4 V. The polarity of the
separated sync is detected by internal integration, then the
polarity is corrected. The polarity information is fed to the
VGA mode detector. If pin 10 is not used, it must be
connected to ground. The separated V_{i sync} signal from
pin10, or the integrated composite sync signal from pin 9
(TTL or video) triggers directly the vertical oscillator.
VGA mode detector and mode output
The three standard VGA modes and a 4th not fixed mode
are decoded by the polarities of the horizontal and the
vertical sync input signals. An external resistor (from V_P to
pin 7) is necessary to match this function. In all three VGA
modes the correct amplitudes are activated. The presence
of the 4th mode is indicated by a HIGH on pin 7. This signal
can be used externally to switch any horizontal or vertical
parameters.
VGA mode detector input
For autosync operation the voltage on pin 7 must be
externally forced to a level of < 50 mV. Vertical amplitude
pre-settings for VGA are then inhibited. The delay time
between vertical trigger pulse and the start of vertical
deflection changes from 575 µs to 300 µs (575 µs is
November 1992
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