PZ3032 Datasheet, PDF (8/14 Pages) NXP Semiconductors – 32 macrocell CPLD

Philips Semiconductors
32 macrocell CPLD
Product specification
PZ3032
DC ELECTRICAL CHARACTERISTICS FOR COMMERCIAL GRADE DEVICES
Commercial: 0°C ≤ T_amb ≤ +70°C; 3.0V ≤ V_DD ≤ 3.6V
SYMBOL
PARAMETER
TEST CONDITIONS
MIN.
MAX.
UNIT
V_IL
Input voltage low
V_DD = 3.0V
0.8
V
V_IH
Input voltage high
V_DD = 3.6V
2.0
V
V_I
Input clamp voltage
V_DD = 3.0V, I_IN = –18mA
–1.2
V
V_OL
Output voltage low
V_DD = 3.0V, I_OL = 8mA
0.5
V
V_OH
Output voltage high
V_DD = 3.0V, I_OH = –8mA
2.4
V
I_IL
Input leakage current low
V_DD = 3.6V (except CKO), V_IN = 0V
–10
10
µA
I_IH
Input leakage current high
V_DD = 3.6V, V_IN = 3.0V
–10
10
µA
I_IL
Clock input leakage current
V_DD = 3.6V, V_IN = 0.4V
–10
10
µA
I_OZL
3-Stated output leakage current low
V_DD = 3.6V, V_IN = 0.4V
–10
10
µA
I_OZH
3-Stated output leakage current high
V_DD = 3.6V, V_IN = 3.0V
–10
10
µA
I_DDQ
Standby current
V_DD = 3.6V, T_amb = 0°C
35
µA
I_DDD1
Dynamic current
V_DD = 3.6V, T_amb = 0°C @ 1MHz
V_DD = 3.6V, T_amb = 0°C @ 50MHz
0.5
mA
18
mA
I_OS
Short circuit output current
1 pin at a time for no longer than 1 second
–5
–100
mA
C_IN
Input pin capacitance
T_amb = 25°C, f = 1MHz
8
pF
C_CLK
Clock input capacitance
T_amb = 25°C, f = 1MHz
5
12
pF
C_I/O
I/O pin capacitance
T_amb = 25°C, f = 1MHz
10
pF
NOTE:
1. This parameter measured with a 16–bit, loadable up/down counter loaded into every logic block, with all outputs enabled and unloaded.
Inputs are tied to V_DD or ground. This parameter guaranteed by design and characterization, not testing.
AC ELECTRICAL CHARACTERISTICS¹ FOR COMMERCIAL GRADE DEVICES
Commercial: 0°C ≤ T_amb ≤ +70°C; 3.0V ≤ V_DD ≤ 3.6V
SYMBOL
PARAMETER
–8
MIN. MAX.
t_{PD_PAL} Propagation delay time, input (or feedback node) to output through PAL
2
8
t_{PD_PLA} Propagation delay time, input (or feedback node) to output through PAL & PLA
3 10.5
t_CO
Clock to out delay time
2
7
t_{SU_PAL} Setup time (from input or feedback node) through PAL
6.5
t_{SU_PLA} Setup time (from input or feedback node) through PAL + PLA
9
t_H
Hold time
0
t_CH
Clock High time
3
t_CL
Clock Low time
3
t_R
Input rise time
20
t_F
Input fall time
20
f_MAX1
Maximum FF toggle rate² (1/t_CH + t_CL)
167
f_MAX2
Maximum internal frequency² (1/t_SUPAL + t_CF)
83
f_MAX3
Maximum external frequency² (1/t_SUPAL + t_CO)
74
t_BUF
Output buffer delay time
1.5
t_{PDF_PAL} Input (or feedback node) to internal feedback node delay time through PAL
6.5
t_{PDF_PLA} Input (or feedback node) to internal feedback node delay time through PAL + PLA
9
t_CF
Clock to internal feedback node delay time
5.5
t_INIT
Delay from valid V_DD to valid reset
50
t_ER
Input to output disable³
15
t_EA
Input to output valid
15
t_RP
Input to register preset
16
t_RR
Input to register reset
19
NOTES:
1. Specifications measured with one output switching. See Figure 6 and Table 3 for derating.
2. This parameter guaranteed by design and characterization, not by test.
3. Output C_L = 5pF.
–10
MIN. MAX.
2 10
3 13
2
9
8.5
11.5
0
4
4
20
20
125
63
57
1.5
8.5
11.5
7.5
50
17
17
18
21
–12
MIN. MAX.
2 12
3 15
2 11
10.5
13.5
0
5
5
20
20
100
50
47
1.5
10.5
13.5
9.5
50
19
19
20
23
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
ns
ns
ns
ns
µs
ns
ns
ns
ns
1997 Feb 20
8