PZ3032 Datasheet, PDF (6/14 Pages) NXP Semiconductors – 32 macrocell CPLD

Philips Semiconductors
32 macrocell CPLD
Product specification
PZ3032
Simple Timing Model
Figure 4 shows the CoolRunner™ Timing Model. The CoolRunner™
timing model looks very much like a 22V10 timing model in that
there are three main timing parameters, including t_PD, t_SU, and t_CO.
In other competing architectures, the user may be able to fit the
design into the CPLD, but is not sure whether system timing
requirements can be met until after the design has been fit into the
device. This is because the timing models of competing
architectures are very complex and include such things as timing
dependencies on the number of parallel expanders borrowed,
sharable expanders, varying number of X and Y routing channels
used, etc. In the XPLA™ architecture, the user knows up front
whether the design will meet system timing requirements. This is
due to the simplicity of the timing model. For example, in the
PZ3032 device, the user knows up front that if a given output uses 5
product terms or less, the t_PD = 8ns, the t_SU = 6.5ns, and the
t_CO = 7.5ns. If an output is using 6 to 37 product terms, an additional
2.5ns must be added to the t_PD and t_SU timing parameters to
account for the time to propagate through the PLA array.
TotalCMOS™ Design Technique
for Fast Zero Power
Philips is the first to offer a TotalCMOS™ CPLD, both in process
technology and design technique. Philips employs a cascade of
CMOS gates to implement its Sum of Products instead of the
traditional sense amp approach. This CMOS gate implementation
allows Philips to offer CPLDs which are both high performance and
low power, breaking the paradigm that to have low power, you must
have low performance. Refer to Figure 5 and Table 2 showing the I_DD
vs. Frequency of our PZ3032 TotalCMOS™ CPLD.
INPUT PIN
t_{PD_PAL} = COMBINATORIAL PAL ONLY
t_{PD_PLA} = COMBINATORIAL PAL + PLA
OUTPUT PIN
INPUT PIN
REGISTERED
t_{SU_PAL} = PAL ONLY
t_{SU_PLA} = PAL + PLA
D
REGISTERED
Q
t_CO
OUTPUT PIN
CLOCK
Figure 4. CoolRunner™ Timing Model
30
25
SP00441
TYPICAL
20
I_DD
15
(mA)
10
5
0
0
10
20
30
40
50
60
70
80
90 100 110 120 130
FREQUENCY (MHz)
Figure 5. I_DD vs. Frequency @ V_DD = 3.3V
Table 2. I_DD vs Frequency
V_DD = 3.3V
FREQ
(MHz)
0
10
20
30
40
50
60
70
80
90
100
110
Typical
I_DD (mA)
0.01 2.37 4.65 6.80 9.06 11.1 13.5 15.5 17.4 20.0 22.1 24.4
SP00443
120 130
26.6 28.5
1997 Feb 20
6