PZ3032 Datasheet, PDF (3/14 Pages) NXP Semiconductors – 32 macrocell CPLD

Philips Semiconductors
32 macrocell CPLD
Product specification
PZ3032
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
PZ3032–8A44
PZ3032–10A44
PZ3032–12A44
PZ3032I10A44
PZ3032I12A44
PZ3032–8BC
PZ3032–10BC
PZ3032–12BC
PZ3032I10BC
PZ3032I12BC
44-pin PLCC, 8ns t_PD
44-pin PLCC, 10ns t_PD
44-pin PLCC, 12ns t_PD
44-pin PLCC, 10ns t_PD
44-pin PLCC, 12ns t_PD
44-pin TQFP, 8ns t_PD,
44-pin TQFP, 10ns t_PD
44-pin TQFP, 12ns t_PD
44-pin TQFP, 10ns t_PD
44-pin TQFP, 12ns t_PD
DESCRIPTION
Commercial temp range, 3.3 volt power supply, ± 10%
Commercial temp range, 3.3 volt power supply, ± 10%
Commercial temp range, 3.3 volt power supply, ± 10%
Industrial temp range, 3.3 volt power supply, ± 10%
Industrial temp range, 3.3 volt power supply, ± 10%
Commercial temp range, 3.3 volt power supply, ± 10%
Commercial temp range, 3.3 volt power supply, ± 10%
Commercial temp range, 3.3 volt power supply, ± 10%
Industrial temp range, 3.3 volt power supply, ± 10%
Industrial temp range, 3.3 volt power supply, ± 10%
DRAWING NUMBER
SOT187-2
SOT187-2
SOT187-2
SOT187-2
SOT187-2
SOT376-1
SOT376-1
SOT376-1
SOT376-1
SOT376-1
XPLA™ ARCHITECTURE
Figure 1 shows a high level block diagram of a 64 macrocell device
implementing the XPLA™ architecture. The XPLA™ architecture
consists of logic blocks that are interconnected by a Zero-power
Interconnect Array (ZIA). The ZIA is a virtual crosspoint switch. Each
logic block is essentially a 36V16 device with 36 inputs from the ZIA
and 16 macrocells. Each logic block also provides 32 ZIA feedback
paths from the macrocells and I/O pins.
From this point of view, this architecture looks like many other CPLD
architectures. What makes the CoolRunner™ family unique is what
is inside each logic block and the design technique used to
implement these logic blocks. The contents of the logic block will be
described next.
Logic Block Architecture
Figure 2 illustrates the logic block architecture. Each logic block
contains control terms, a PAL array, a PLA array, and 16 macrocells.
The 6 control terms can individually be configured as either SUM or
PRODUCT terms, and are used to control the preset/reset and
output enables of the 16 macrocells’ flip-flops. The PAL array
consists of a programmable AND array with a fixed OR array, while
the PLA array consists of a programmable AND array with a
programmable OR array. The PAL array provides a high speed path
through the array, while the PLA array provides increased product
term density.
Each macrocell has 5 dedicated product terms from the PAL array.
The pin-to-pin t_PD of the PZ3032 device through the PAL array is
8ns. This performance is the fastest 3 volt CPLD available today. If a
macrocell needs more than 5 product terms, it simply gets the
additional product terms from the PLA array. The PLA array consists
of 32 product terms, which are available for use by all 16
macrocells. The additional propagation delay incurred by a
macrocell using 1 or all 32 PLA product terms is just 2.5ns. So the
total pin-to-pin t_PD for the PZ3032 using 6 to 37 product terms is
10.5ns (8ns for the PAL + 2.5ns for the PLA).
MC0
MC1
LOGIC
36
I/O
BLOCK
MC15
16
16
MC0
I/O
MC1
LOGIC
36
BLOCK
MC15
16
16
MC0
36
LOGIC
MC1
BLOCK
I/O
MC15
16
16
ZIA
MC0
36
LOGIC
MC1
BLOCK
I/O
MC15
16
16
Figure 1. Philips XPLA CPLD Architecture
SP00439
1997 Feb 20
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