74HC193 Datasheet, PDF (8/13 Pages) NXP Semiconductors – Presettable synchronous 4-bit binary up/down counter

Philips Semiconductors
Presettable synchronous 4-bit binary
up/down counter
Product specification
74HC/HCT193
T_amb (°C)
TEST CONDITIONS
SYMBOL PARAMETER
74HC
+25
−40 to +85
−40 to +125
UNIT
V_CC
(V)
WAVEFORMS
min. typ. max. min. max. min. max.
t_W
master reset pulse width 100 25
125
150
ns 2.0 Fig.10
HIGH
20 9
25
30
4.5
17 7
21
26
6.0
t_W
parallel load pulse width 100 19
125
150
ns 2.0 Fig.9
LOW
20 7
25
30
4.5
17 6
21
26
6.0
t_rem
removal time
50 8
65
75
ns 2.0 Fig.9
PL to CP_U, CP_D
10 3
13
15
4.5
92
11
13
6.0
t_rem
removal time
50 0
65
75
ns 2.0 Fig.10
MR to CP_U, CP_D
10 0
13
15
4.5
90
11
13
6.0
t_su
set-up time
D_n to PL
80 22
100
120
ns 2.0 Fig.11 note:
16 8
20
24
14 6
17
20
4.5 CP_U = CP_D =
6.0 HIGH
t_h
hold time
D_n to PL
0 −14
0
0
ns 2.0 Fig.11
0 −5
0
0
4.5
0 −4
0
0
6.0
t_h
hold time
CP_U to CP_D,
CP_D to CP_U
80 22
100
120
ns 2.0 Fig.13
16 8
20
24
4.5
86
17
20
6.0
f_max
maximum up, down clock 4.0 13.5
3.2
2.6
MHz 2.0 Fig.7
pulse frequency
20 41
16
13
4.5
24 49
19
15
6.0
December 1990
8