74HC193 Datasheet, PDF (12/13 Pages) NXP Semiconductors – Presettable synchronous 4-bit binary up/down counter

Philips Semiconductors
Presettable synchronous 4-bit binary
up/down counter
Product specification
74HC/HCT193
(1) HC : V_M = 50%; V_I = GND to V_CC.
HCT: V_M = 1.3V; V_I = GND to 3 V.
Fig.10 Waveforms showing the master reset input (MR) pulse width, MR to Q_n propagation delays, MR to CP_U,
CP_D removal time and output transition times.
The shaded areas indicate when the input is permitted to
change for predictable output performance.
(1) HC : V_M = 50%; V_I = GND to V_CC.
HCT: V_M = 1.3V; V_I = GND to 3 V.
Fig.11 Waveforms showing the data input (D_n) to parallel load input (PL) set-up and hold times.
(1) HC : V_M = 50%; V_I = GND to V_CC.
HCT: V_M = 1.3V; V_I = GND to 3 V.
Fig.12 Waveforms showing the data input (D_n), parallel load input (PL) and the master reset input (MR) to the
terminal count outputs (TC_U, TC_D) propagation delays.
(1) HC : V_M = 50%; V_I = GND to V_CC.
HCT: V_M = 1.3V; V_I = GND to 3 V.
Fig.13 Waveforms showing the CP_U to CP_D or CP_D to CP_U hold times.
December 1990
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