74HC193 Datasheet, PDF (10/13 Pages) NXP Semiconductors – Presettable synchronous 4-bit binary up/down counter

Philips Semiconductors
Presettable synchronous 4-bit binary
up/down counter
Product specification
74HC/HCT193
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; t_r = t_f = 6 ns; C_L = 50 pF
SYMBOL PARAMETER
t_PHL/ t_PLH
t_PHL/ t_PLH
t_PHL/ t_PLH
t_PHL/ t_PLH
t_PHL
t_PHL/ t_PLH
t_PHL/ t_PLH
t_PHL/ t_PLH
t_PHL/ t_PLH
t_THL/ t_TLH
propagation delay
CP_U, CP_D to Q_n
propagation delay
CP_U to TC_U
propagation delay
CP_D to TC_D
propagation delay
PL to Q_n
propagation delay
MR to Q_n
propagation delay
D_n to Q_n
propagation delay
PL to TC_U, PL to TC_D
propagation delay
MR to TC_U, MR to TC_D
propagation delay
D_n to TC_U, D_n to TC_D
output transition time
T_amb (°C)
TEST CONDITIONS
74HCT
+25
−40 to +85
−40 to +125
UNIT
V_CC
(V)
WAVEFORMS
min. typ. max. min. max. min. max.
23 43
54
65 ns 4.5 Fig.7
15 27
34
41 ns 4.5 Fig.8
15 27
34
41 ns 4.5 Fig.8
26 46
58
69 ns 4.5 Fig.9
22 40
50
60 ns 4.5 Fig.10
27 46
58
69 ns 4.5 Fig.9
31 55
69
83 ns 4.5 Fig.12
29 55
69
83 ns 4.5 Fig.12
32 58
73
87 ns 4.5 Fig.12
7 15
19
22 ns 4.5 Fig.10
t_W
up, down clock pulse width 25 11
31
38
ns 4.5 Fig.7
HIGH or LOW
t_W
master reset pulse width 20 7
HIGH
25
30
ns 4.5 Fig.10
t_W
parallel load pulse width 20 8
LOW
25
30
ns 4.5 Fig.9
t_rem
removal time
PL to CP_U, CP_D
t_rem
removal time
MR to CP_U, CP_D
t_su
set-up time
D_n to PL
10 2
10 0
16 8
13
15
ns 4.5 Fig.9
13
15
ns 4.5 Fig.10
20
24
ns 4.5 Fig.11 note:
CP_U = CP_D =
HIGH
t_h
hold time
D_n to PL
0 −6
0
0
ns 4.5 Fig.11
t_h
hold time
16 7
CP_U to CP_D, CP_D to CP_U
20
24
ns 4.5 Fig.13
f_max
maximum up, down clock 20 43
16
13
MHz 4.5 Fig.7
pulse frequency
December 1990
10