74HC192 Datasheet, PDF (8/13 Pages) NXP Semiconductors – Presettable synchronous BCD decade up/down counter

Philips Semiconductors
Presettable synchronous BCD decade
up/down counter
Product specification
74HC/HCT192
T_amb (°C)
TEST CONDITIONS
SYMBOL
PARAMETER
min.
+25
typ. max.
74HC
−40 to +85 −40 to +125
min. max. min. max.
UNIT _VCC
(V)
WAVEFORMS
t_W
up clock pulse width
120 39
HIGH or LOW
24 14
20 11
150
180
30
36
26
31
ns 2.0 Fig.7
4.5
6.0
t_W
down clock pulse width 140 50
HIGH or LOW
28 18
24 14
175
210
35
42
30
36
ns 2.0 Fig.7
4.5
6.0
t_W
master reset pulse width 80 22
HIGH
16 8
14 6
100
120
20
24
17
20
ns 2.0 Fig.10
4.5
6.0
t_W
parallel load pulse width 80 22
LOW
16 8
14 6
100
120
20
24
17
20
ns 2.0 Fig.9
4.5
6.0
t_rem
removal time
PL to CP_U, CP_D
50 3
10 1
91
65
75
13
15
11
13
ns 2.0 Fig.9
4.5
6.0
t_rem
removal time
MR to CP_U, CP_D
50 0
10 0
90
65
75
13
15
11
13
ns 2.0 Fig.10
4.5
6.0
t_su
set-up time
D_n to PL
80 22
16 8
14 6
100
120
20
24
17
20
ns 2.0 Fig.11 note:
4.5 CP_U = CP_D =
6.0 HIGH
t_h
hold time
D_n to PL
0 −14
0
0
0 −5
0
0
0 −4
0
0
ns 2.0 Fig.11
4.5
6.0
t_h
hold time
CP_U to CP_D,
CP_D to CP_U
80 19
16 7
14 6
f_max
maximum up, down clock 4.0 12
pulse frequency
20 36
24 43
100
120
20
24
17
20
3.2
2.6
16
13
19
15
ns 2.0 Fig.13
4.5
6.0
MHz 2.0 Fig.7
4.5
6.0
December 1990
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