74HC192 Datasheet, PDF (10/13 Pages) NXP Semiconductors – Presettable synchronous BCD decade up/down counter

Philips Semiconductors
Presettable synchronous BCD decade
up/down counter
Product specification
74HC/HCT192
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; t_r = t_f = 6 ns; C_L = 50 pF
SYMBOL
PARAMETER
t_PHL/ t_PLH
t_PHL/ t_PLH
t_PHL/ t_PLH
t_PHL/ t_PLH
t_PHL
t_PHL/ t_PLH
t_PHL/ t_PLH
t_PHL/ t_PLH
t_PHL/ t_PLH
t_THL/ t_TLH
propagation delay
CP_U, CP_D to Q_n
propagation delay
CP_U to TC_U
propagation delay
CP_D to TC_D
propagation delay
PL to Q_n
propagation delay
MR to Q_n
propagation delay
D_n to Q_n
propagation delay
PL to TC_U, PL to TC_D
propagation delay
MR to TC_U, MR to TC_D
propagation delay
D_n to TC_U, D_n to TC_D
output transition time
T_amb (°C)
TEST CONDITIONS
74HCT
+25
−40 to +85
−40 to +125
UNIT
V_CC
(V)
WAVEFORMS
min. typ. max. min. max. min. max.
23 43
54
65 ns 4.5 Fig.7
16 30
38
45 ns 4.5 Fig.8
17 30
38
45 ns 4.5 Fig.8
28 46
58
69 ns 4.5 Fig.9
24 40
50
60 ns 4.5 Fig.10
36 62
78
93 ns 4.5 Fig.9
36 64
80
96 ns 4.5 Fig.12
36 64
80
96 ns 4.5 Fig.12
33 58
73
87 ns 4.5 Fig.12
7 15
19
22 ns 4.5 Fig.10
t_W
up, down clock pulse width 25 14
31
38
HIGH or LOW
t_W
master reset pulse width 16 6
HIGH
20
24
t_W
parallel load pulse width 20 10
25
30
LOW
t_rem
removal time
PL to CP_U, CP_D
t_rem
removal time
MR to CP_U, CP_D
t_su
set-up time
D_n to PL
10 1
10 2
16 8
13
15
13
15
20
24
t_h
hold time
D_n to PL
0 −6
0
0
t_h
hold time
20 9
CP_U to CP_D, CP_D to CP_U
25
30
f_max
maximum up, down clock 20 41
16
13
pulse frequency
ns 4.5 Fig.7
ns 4.5 Fig.10
ns 4.5 Fig.9
ns 4.5 Fig.9
ns 4.5 Fig.10
ns 4.5 Fig.11 note:
CP_U = CP_D =
HIGH
ns 4.5 Fig.11
ns 4.5 Fig.13
MHz 4.5 Fig.7
December 1990
10