74HC192 Datasheet, PDF (3/13 Pages) NXP Semiconductors – Presettable synchronous BCD decade up/down counter

Philips Semiconductors
Presettable synchronous BCD decade
up/down counter
QUICK REFERENCE DATA
GND = 0 V; T_amb = 25 °C; t_r = t_f = 6 ns
SYMBOL
PARAMETER
CONDITIONS
t_PHL/ t_PLH
f_max
C_I
C_PD
propagation delay CP_D, CP_U to Q_n
maximum clock frequency
input capacitance
power dissipation capacitance per package
C_L = 15 pF; V_CC = 5 V
notes 1 and 2
Notes
1. C_PD is used to determine the dynamic power dissipation (P_D in µW):
P_D = C_PD × V_CC2 × f_i + ∑ (C_L × V_CC2 × f_o) where:
f_i = input frequency in MHz
f_o = output frequency in MHz
∑ (C_L × V_CC2 × f_o) = sum of outputs
C_L = output load capacitance in pF
V_CC = supply voltage in V
2. For HC the condition is V_I = GND to V_CC
For HCT the condition is V_I = GND to V_CC −1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
Product specification
74HC/HCT192
TYPICAL
HC
HCT
20
20
40
45
3.5
3.5
24
28
UNIT
ns
MHz
pF
pF
December 1990
3