74ABTL3205 Datasheet, PDF (8/14 Pages) NXP Semiconductors – 10-bit BTL transceiver with registers

Philips Semiconductors
10-bit BTL transceiver with registers
Product specification
74ABTL3205
LIVE INSERTION SPECIFICATIONS
SYMBOL
PARAMETER
V_BIASV
I_BIASV
Ǹ_Bn
Bias pin DC current
Bias pin DC current
Bus voltage during prebias
V_CC = 0 to 5.25V, Bn = 0 to 2.0 V
V_CC = 0 to 4.75 V, Bn = 0 to 2.0V,
Bias V = 4.5 to 5.5V
V_CC = 4.5 to 5.5V, Bn = 0 to 2.0 V,
Bias V = 4.5 to 5.5V
B0 – B8 = 0V, Bias V = 5.0V
LIMITS
MIN
NOM
MAX
4.5
5.5
1
10
1.62
2.1
UNIT
V
mA
µA
V
AC ELECTRICAL CHARACTERISTICS
A PORT LIMITS
SYMBOL
PARAMETER
TEST
CONDITION
T_amb = +25°C
V_CC = 5V
C_L = 50pF, C_L = 500Ω
MIN
TYP MAX
T_amb = –40°C to +85°C
V_CC = 5V ± 10%
C_L = 50pF, C_L = 500Ω
MIN
MAX
UNIT
t_PLH
Propagation delay
t_PHL
Bn to An
Waveform 2
2.0
3.6
6.5
2.0
1.8
3.5
6.1
1.8
7.3
6.7
ns
t_PLH
Propagation delay,
t_PHL
BCLK1 to ACLK1
Waveform 2
2.0
3.8
6.5
2.0
1.8
3.6
6.1
1.8
7.3
ns
6.7
t_PLH
Propagation delay
t_PHL
BCLK1 to ACLKin
Waveform 2
2.0
3.7
6.5
2.0
1.8
3.7
6.1
1.8
7.3
ns
6.7
t_PLH
Propagation delay
t_PHL
BCLK2 to ACLK2
Waveform 2
2.0
3.7
6.5
2.0
1.8
3.9
6.1
1.8
7.3
ns
6.7
t_PLH
Propagation delay
t_PHL
BCLK2 to AFP
Waveform 2
2.0
3.8
6.5
2.0
1.8
3.9
6.1
1.8
7.3
ns
6.7
t_PZH
Output Enable time
t_PLZ
OEA1, OEA2, IEA to An
Waveform 1, 2
2.0
3.8
6.5
2.0
1.8
2.5
6.1
1.8
7.3
ns
6.7
t_PHZ
Output Disable time
t_PLZ
OEA1, OEA2, IEA to An
Waveform 4, 5
1.6
2.5
5.6
1.4
2.0
3.3
7.8
1.8
5.7
ns
8.2
t_TLH
Output transition time, An Port
t_THL
10% to 90%, 90% to 10%
Test Circuit and
Waveforms
3.0
7.0
ns
1.7
4.0
t_SK(p)
Pulse skew²
|t_PHL – t_PLH| _MAX
Waveform 3
2.0
ns
NOTES:
1. | t_PN actual – t_PM actual | for any data input to output path compared to any other data input to output path where N and M are either LH or
HL. Skew times are valid only under same test conditions (temperature, V_CC, loading, etc.).
2. t_SK(p) is used to quantify duty cycle characteristics. In essence it compares the input signal duty cycle to the corresponding output signal
duty cycle. (50MHz input frequency and 50% duty cycle, tested on data paths only).
1995 Jun 16
8