74ABTL3205 Datasheet, PDF (3/14 Pages) NXP Semiconductors – 10-bit BTL transceiver with registers

Philips Semiconductors
10-bit BTL transceiver with registers
Product specification
74ABTL3205
PIN CONFIGURATION
52 51 50 49 48 47 46 45 44 43 42 41 40
TTL Gnd 1
A0 2
A1 3
TTL GND 4
A2 5
A3 6
TTL GND 7
AClk2 8
TTL GND 9
A4 10
A5 11
TTL GND 12
A6 13
39
38
37
36
35
34
33
32
31
30
29
28
27
14 15 16 17 18 19 20 21 22 23 24 25 26
BUS GND
B0
B1
BUS GND
B2
B3
BUS GND
BClk2
BUS GND
B4
B5
BUS GND
B6
PIN DESCRIPTION
SYMBOL
FUNCTION
OEA1
Output enable data receiver group 1
OEA2
Output enable data receiver group 2
OEB
Output enable data transmitter
IEA
Output enable clock and framepulse receiver
M/S
Master/Slave select:
L:
Master, enable clock transmitter
H:
Slave, disable clock transmitter
Mode
Low:
High:
Data through mode
Registered data mode
Power Up
Power up mode, held low during power up to
disable clock and data transmitters
Recmode
Enables receiver
Tranmode
Enables transmitter
AClk1
Clock or data path
AClkln
IEA = H → Input for busclock
IEA = L → Output for busclock
A0..A3
data group 1
AClk2
Clock or data path
AFPIn
Alternate data path
APAR
Alternate data path
A4..A7
data group 2
BClk1
Clock or data path
B0..B3
data group 1
BClk2
Clock or data path
B4..B7
data group 2
1995 Jun 16
3
SA00138
ASSERTION
Low
Low
Low
Low
I/O
Input
Input
Input
Input
Input
LOGIC
TTL
TTL
TTL
TTL
TTL
Input
TTL
Low
High
High
Input
TTL
Input
TTL
Input
TTL
I/O
TTL
I/O
TTL
I/O
TTL
I/O
TTL
Output
TTL
Input
TTL
I/O
TTL
I/O
BTL
I/O
BTL
I/O
BTL
I/O
BTL