UMA1018M Datasheet, PDF (7/20 Pages) NXP Semiconductors – Low-voltage dual frequency synthesizer for radio telephones

Philips Semiconductors
Low-voltage dual frequency
synthesizer for radio telephones
Product specification
UMA1018M
Table 4 Fast and normal charge pumps current ratio (note 1)
CR1
0
0
1
1
CR0
0
1
0
1
I_CPA
4 × I_SET
4 × I_SET
4 × I_SET
4 × I_SET
I_CPP
4 × I_SET
4 × I_SET
2 × I_SET
2 × I_SET
Note
1. I_SET = _R--V---e-¹--_x4--_t ; common bias current for charge pumps and DAC.
I_CPPF
16 × I_SET
32 × I_SET
24 × I_SET
32 × I_SET
Table 5 Power-down modes
AON
0
0
0
1
1
1
PON
0
1
1
0
1
1
FAST
X
0
1
X
0
1
PRINCIPAL
DIVIDERS
OFF
ON
ON
OFF
ON
ON
AUXILIARY
DIVIDERS
OFF
OFF
OFF
ON
ON
ON
PUMP
CPA
OFF
OFF
OFF
ON
ON
ON
PUMP
CPP
OFF
ON
ON
OFF
ON
ON
PUMP
CPPF
OFF
OFF
ON
OFF
OFF
ON
I_CPPF : I_CPP
4:1
8:1
12 : 1
16 : 1
DAC AND BIAS
OFF
ON
ON
ON
ON
ON
Digital-to-analog converter
The 7-bits loaded via the bus into the appropriate latch
drive a digital-to-analog converter. The internal current is
scaled by the external resistance (R_ext) at pin I_SET, similar
to the charge pumps. The nominal full-scale current is
2 × I_SET. The output current is mirrored to produce a
full-scale voltage into a user-defined ground referenced
resistance, thereby allowing optimum swing from power
supply rails within the 2.7 to 5.5 V limits. The band gap
reference voltage at pin I_SET is temperature and supply
independent. The DAC signal is monotonic across the full
range of digital input codes to enable fine adjustment of
other system blocks. The typical settling time for full-scale
switching is 400 ns into a 12 kΩ // 20 pF load. DAC
functionality is neither tested nor guaranteed on
UMA1018M versions with the /S1 suffix.
Power-down modes
The action of the control inputs on the state of internal
blocks is defined by Table 5.
It should be noted that in Table 5, PON and AON can be
either the software or hardware power-down signals.
The dividers are ON when both hardware and software
power-down signals are at logic 1.
When either synthesizer is reactivated after power-down
the main and reference dividers of that synthesizer are
synchronized to avoid the possibility of random phase
errors on power-up.
1995 Jun 27
7