UMA1018M Datasheet, PDF (11/20 Pages) NXP Semiconductors – Low-voltage dual frequency synthesizer for radio telephones

Philips Semiconductors
Low-voltage dual frequency
synthesizer for radio telephones
Product specification
UMA1018M
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX. UNIT
DAC output signal levels; pin 10; R_ext = 12 to 24 kΩ
I_DAC
V₁₀
I_10min
I_monot
DAC full scale output current
output voltage compliance
minimum DAC current
worst case monotonicity test:
∆I × _2-----×-1---2-I--_S-8--_E----_T-
all codes
00 code
note 1
1.5 × I_SET 2 × I_SET
0
−
−
2
0.1
−
2.5 × I_SET mA
V_DD − 0.4 V
5
µA
1.9
Lock detect output signal; pin 20; open-drain output
V_OL
LOW level output voltage
I_sink = 0.4 mA
−
−
0.4
V
Note
1. ∆I is the change in DAC output current when making the code transitions: 3FH/40H or 1FH/20H.
SERIAL BUS TIMING CHARACTERISTICS
V_DD = V_CC = 3 V; T_amb = 25 °C unless otherwise specified.
SYMBOL
PARAMETER
MIN.
TYP.
MAX. UNIT
Serial programming clock; CLK
t_r
input rise time
t_f
input fall time
T_cy
clock period
Enable programming; E
t_START
t_END
t_W
t_SU;E
delay to rising clock edge
delay from last falling clock edge
minimum inactive pulse width
enable set-up time to next clock edge
Register serial input data; DATA
t_SU;DAT
t_HD;DAT
input data to clock set-up time
input data to clock hold time
−
10
40
ns
−
10
40
ns
100
−
−
ns
40
−
−
ns
−20
−
−
ns
4000⁽¹⁾ −
−
ns
20
−
−
ns
20
−
−
ns
20
−
−
ns
Note
1. The minimum pulse width (t_W) can be smaller than 4 µs provided all the following conditions are satisfied:
a) Principal main divider input frequency f_VCO > ^2--t--5_W---6--
b) Auxiliary main divider input frequency f_AI > ^3-t--_W-2--
c) Reference divider input frequency f_XTAL > _t--3W---
1995 Jun 27
11