UMA1018M Datasheet, PDF (4/20 Pages) NXP Semiconductors – Low-voltage dual frequency synthesizer for radio telephones

Philips Semiconductors
Low-voltage dual frequency
synthesizer for radio telephones
Product specification
UMA1018M
PINNING
SYMBOL PIN
DESCRIPTION
FAST
1 control input to speed-up main
synthesizer
CPPF
2 principal synthesizer speed-up
charge-pump output
CPP
3 principal synthesizer normal
charge-pump output
V_DD1
V_DD2
PRI
4 digital power supply 1
5 digital power supply 2
6 1 GHz principal synthesizer
frequency input
DGND
7 digital ground
f_XTAL
8 common crystal frequency input from
TCXO
PON
9 principal synthesizer power-on input
DOUT
10 7-bit digital-to-analog output
CLK
11 Programming bus clock input
DATA
12 programming bus data input
E
13 programming bus enable input
(active LOW)
I_SET
14 regulator pin to set the charge-pump
currents
AUX
15 auxiliary synthesizer frequency input
AGND
16 analog ground
CPA
17 auxiliary synthesizer charge-pump
output
V_CC
18 supply for charge-pump and DAC
circuits
AON
19 auxiliary synthesizer power-on input
LOCK
20 in-lock detect output (main PLL);
test mode output
Fig.2 Pin configuration.
FUNCTIONAL DESCRIPTION
Principal synthesizer
Programmable reference and main dividers drive the
principal PLL phase detector. Two charge pumps produce
phase error current pulses for integration in an external
loop filter. A hardwired power-down input PON (pin 9)
ensures that the dividers and phase comparator circuits
can be disabled.
The PRI input (pin 6) drives a pre-amplifier to provide the
clock to the first divider stage. The pre-amplifier has a high
input impedance, dominated by pin and pad capacitance.
The circuit operates with signal levels from 50 mV up to
225 mV (RMS), and at frequencies as high as 1.25 GHz.
The high frequency divider circuits use bipolar transistors,
slower bits are CMOS. Divider ratios (512 to 131 071)
allow a 1 MHz phase comparison with a 500 MHz RF
input, and a 10 kHz phase comparison with a 1.25 GHz RF
input.
The reference and main divider outputs are connected to
a phase/frequency detector that controls two charge
pumps. The two pumps have a common bias-setting
current that is set by an external resistance. The ratio
between currents in fast and normal operating modes can
be programmed via the 3-wire serial bus. The low current
pump remains active except in power-down.
1995 Jun 27
4