UMA1015M Datasheet, PDF (7/24 Pages) NXP Semiconductors – Low-power dual frequency synthesizer for radio communications

Philips Semiconductors
Low-power dual frequency synthesizer
for radio communications
Product specification
UMA1015M
Power-down modes
The device can be powered down either via pin HPD
(active LOW = power-down) or via the serial bus (bits
SPDA and SPDB, logic 0 = power-down). The
synthesizers are powered up when both hardware and
software Power-down signals are at logic 1. When only
one synthesizer is powered down, the functions common
to both will be maintained. When both synthesizers are
switched off, only the voltage doubler (if enabled) will
remain active drawing a reduced current. An internal
oscillator will drive the doubler in this situation. If both
synthesizers have been in a power-down condition, then
when one or both synthesizers are reactivated, the
reference and main dividers restart in such a way as to
avoid large random phase errors at the phase comparator.
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134).
SYMBOL
V_DD1, V_DD2
V_CC
∆V_CC-DD
V_n
V_{3, 17}
∆V_GND
T_stg
T_amb
PARAMETER
MIN.
DC range of digital power supply voltage with respect −0.3
to DGND
DC charge pump supply voltage with respect to AGND −0.3
difference in voltage between V_CC and V_DD1, V_DD2
−0.3
DC voltage at pins 1, 2, 5, 6, 8 to 15, 19 and 20 with −0.3
respect to DGND
DC voltage at pins 3 and 17 with respect to AGND
−0.3
difference in voltage between AGND and DGND
−0.3
(these pins should be connected together)
storage temperature
−55
operating ambient temperature
−30
MAX.
+6.0
UNIT
V
+6.0
V
+6.0
V
V_DD1 + 0.3 V
V_CC + 0.3 V
+0.3
V
+125
°C
+85
°C
HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling MOS devices.
1995 Jun 22
7