TDA8776 Datasheet, PDF (7/20 Pages) NXP Semiconductors – 10-bit, 500 Msps Digital-to-Analog Converter DAC

Philips Semiconductors
10-bit, 500 Msps Digital-to-Analog
Converter (DAC)
Product specification
TDA8776
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
Switching characteristics (f_clk = 500 MHz); notes 5 and 6; see Figs 8 and 9
t_SU;DAT
t_HD;DAT
t_PD
t_S1
t_S2
t_d
data set-up time
data hold time
propagation delay time
settling time
settling time
input to 50% output delay time
10% to 90% full scale
change to ±1 LSB
−
400 500 ps
100 150 −
ps
−
0.8 0.9 ns
−
0.5 −
ns
−
2.0 −
ns
−
1.4 1.5 ns
Output transients; glitches (f_clk = 500 MHz); note 7; see Fig.10
E_g
differential glitch energy from code transition 511 to 512
−
1
2
pV.s
Notes
1. D0 to D9 connected to either HIGH or LOW level, CLK is HIGH and CLK is LOW.
2. The analog output voltages (V_OUT and V_OUT) are negative with respect to AGND (see Table 1). The external output
resistance between AGND and each of these outputs is typically 50 Ω.
3. Due to on-chip regulator behaviour a warm-up time is necessary to reach optimal performances; a typical time is
1 minute.
4. Devices with higher SFDR (min.) can be delivered on request.
5. The worst case characteristics are obtained at the transition from input code 0 to 1023 and if an external load
impedance greater than 50 Ω is connected between V_OUT or V_OUT and AGND in parallel with the external 50 Ω load.
The specified values have been measured directly on a 50 Ω load between V_OUT and AGND. No further load
impedance between V_OUT and AGND has been applied. All input data is latched at the falling edge of the clock.
6. The data set-up (t_SU;DAT) is the minimum period preceding the falling edge of the clock that the input data must be
stable in order to be correctly registered. A negative set-up time indicates that the data may be initiated after the
falling edge of the clock and still be recognized. The data hold time (t_HD;DAT) is the minimum period following the
falling edge of the clock that the input data must be stable in order to be correctly registered. A negative hold time
indicates that the data may be released prior to the falling edge of the clock and still be recognized.
7. The definition of glitch energy and the measurement set-up are shown in Fig.10. The glitch energy is measured at
the input transition between code 511 to 512.
Table 1 Input coding and DAC output voltages (typical values; referenced to AGND regardless of the offset voltage)
CODE
BINARY INPUT DATA
DAC OUTPUT
VOLTAGES (V)
Z_L = 50 Ω
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
V_OUT
V_OUT
0
0
0
0
0
0
0
0
0
0
0
0
−1.0
1
0
0
0
0
0
0
0
0
0
1 −0.0010 −0.9990
.
.
.
.
.
.
.
.
.
.
.
.
.
512
1
0
0
0
0
0
0
0
0
0
−0.5
−0.5
.
.
.
.
.
.
.
.
.
.
.
.
.
1022
1
1
1
1
1
1
1
1
1
0 −0.9990 −0.0010
1023
1
1
1
1
1
1
1
1
1
1
−1.0
0
1996 Jun 04
7