80C528 Datasheet, PDF (7/26 Pages) NXP Semiconductors – CMOS single-chip 8-bit microcontroller

Philips Semiconductors
CMOS single-chip 8-bit microcontrollers
Product specification
80C528/83C528
PIN DESCRIPTION
PIN NO.
MNEMONIC DIP SDIL LCC QFP TYPE
NAME AND FUNCTION
V_SS
20
21
22
16
I Ground: circuit ground potential.
V_DD
40
42
44
38
I Power Supply: +5V power supply pin during normal operation, Idle mode and
Power-down mode.
P0.0–0.7
39–32 41–34 43–36 37–30 I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s
written to them float and can be used as high-impedance inputs. Port 0 is also the
multiplexed low-order address and data bus during accesses to external program
and data memory. In this application, it uses strong internal pull-ups when emitting
1s.
P1.0–P1.7
1–8 1–8 2–9 40–44 I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups, except P1.6 and
1–3
P1.7 which have open drain. Port 1 pins that have 1s written to them are pulled high
by the internal pull-ups and can be used as inputs. As inputs, port 1 pins that are
externally pulled low will source current because of the internal pull-ups. (See DC
Electrical Characteristics: I_IL). Port 1 can sink/source one TTL (4 LSTTL) inputs.
1
1
2
40
I T2 (P1.0): Timer/counter 2 external count input (following edge triggered).
2
2
3
41
I T2EX (P1.1): Timer/counter 2 trigger input.
7
7
8
2
I/O SCL (P1.6): I²C serial port clock line.
8
8
9
3
I/O SDA (P1.7): I²C serial port data line.
P2.0–P2.7
21–28 22–29 24–31 18–25 I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that
have 1s written to them are pulled high by the internal pull-ups and can be used as
inputs. As inputs, port 2 pins that are externally being pulled low will source current
because of the internal pull-ups. (See DC Electrical Characteristics: I_IL). Port 2
emits the high-order address byte during fetches from external program memory
and during accesses to external data memory that use 16-bit addresses (MOVX
@DPTR). In this application, it uses strong internal pull-ups when emitting 1s.
During accesses to external data memory that use 8-bit addresses (MOV @Ri), port
2 emits the contents of the P2 special function register.
P3.0–P3.7
10–17 10–18 11, 5,
(11=NC) 13–19 7–13
10
10
11
5
11
12
13
7
12
13
14
8
13
14
15
9
14
15
16
10
15
16
17
11
16
17
18
12
17
18
19
13
I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that
have 1s written to them are pulled high by the internal pull-ups and can be used as
inputs. As inputs, port 3 pins that are externally being pulled low will source current
because of the pull-ups. (See DC Electrical Characteristics: I_IL). Port 3 also serves
the special features of the SC80C51 family, as listed below:
I RxD (P3.0): Serial input port
O TxD (P3.1): Serial output port
I INT0 (P3.2): External interrupt
I INT1 (P3.3): External interrupt
I T0 (P3.4): Timer 0 external input
I T1 (P3.5): Timer 1 external input
O WR (P3.6): External data memory write strobe
O RD (P3.7): External data memory read strobe
RST
9
9
10
4
I/O Reset: A high on this pin for two machine cycles while the oscillator is running,
resets the device. An internal diffused resistor to V_SS permits a power-on reset
using only an external capacitor to V_DD. After a watchdog timer overflow, this pin is
pulled high while the internal reset signal is active.
ALE
30
31
33
27
I/O Address Latch Enable: Output pulse for latching the low byte of the address
during an access to external memory. In normal operation, ALE is emitted at a
constant rate of 1/6 the oscillator frequency, and can be used for external timing or
clocking. Note that one ALE pulse is skipped during each access to external data
memory.
PSEN
EA
29
30
32
26
O Program Store Enable: The read strobe to external program memory. When the
device is executing code from the external program memory, PSEN is activated
twice each machine cycle, except that two PSEN activations are skipped during
each access to external data memory. PSEN is not activated during fetches from
internal program memory.
31
33
35
29
I External Access Enable: EA must be externally held low during RESET to enable
the device to fetch code from external program memory locations 0000H to 7FFFH.
If EA is held high during RESET, the device executes from internal program memory
unless the program counter contains an address greater than 7FFFH. EA is don’t
care after RESET.
XTAL1
19
20
21
15
I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock
generator circuits.
XTAL2
18
19
20
14
O Crystal 2: Output from the inverting oscillator amplifier.
1995 Feb 02
7