80C528 Datasheet, PDF (15/26 Pages) NXP Semiconductors – CMOS single-chip 8-bit microcontroller

Philips Semiconductors
CMOS single-chip 8-bit microcontrollers
Product specification
80C528/83C528
AC ELECTRICAL CHARACTERISTICS – I²C INTERFACE
SYMBOL
PARAMETER
INPUT
OUTPUT
I²C SPECIFICATION
SCL TIMING CHARACTERISTICS
t_HD;STA
START condition hold time
t_LOW
SCL LOW time
t_HIGH
SCL HIGH time
t_RC
SCL rise time
t_FC
SCL fall time
SDA TIMING CHARACTERISTICS
≥ 14 t_CLCL1
≥ 16 t_CLCL
≥ 14 t_CLCL1
≤ 1µs⁴
≤ 0.3µs⁴
Note 2
Note 2
≥ 80 t_CLCL3
Note 5
≤ 0.3µs ⁶
≥ 4.0µs
≥ 4.7µs
≥ 4.0µs
≤ 1.0µs
≤ 0.3µs
t_SU;DAT1 Data set-up time
≥ 250ns
Note 2
≥ 250ns
t_HD;DAT
Data hold time
≥ 0ns
Note 2
≥ 0ns
t_SU;STA
Repeated START set-up time
≥ 14 t_CLCL1
Note 2
≥ 4.7µs
t_SU;STO STOP condition set-up time
≥ 14 t_CLCL1
Note 2
≥ 4.0µs
t_BUF
Bus free time
≥ 14 t_CLCL1
Note 2
≥ 4.7µs
t_RD
SDA rise time
≤ 1µs⁴
Note 5
≤ 1.0µs
t_FD
SDA fall time
≤ 0.3µs⁴
≤ 0.3µs ⁶
≤ 0.3µs
NOTES:
1. At f_CLK = 3.5MHz, this evaluates to 14 × 286ns = 4µs, i.e., the bit-level I²C interface can respond to the I²C protocol for f_CLK ≥ 3.5MHz.
2. This parameter is determined by the user software, it has to comply with the I²C.
3. This value gives the autoclock pulse length which meets the I²C specification for the specified XTAL clock frequency range. Alternatively, the
SCL pulse may be timed by software.
4. Spikes on SDA and SCL lines with a duration of less than 4 × f_CLK will be filtered out.
5. The rise time is determined by the external bus line capacitance and pull-up resistor, it must be ≤ 1µs.
6. The maximum capacitance on bus lines SDA and SCL is 400pF.
1995 Feb 02
15