80C528 Datasheet, PDF (2/26 Pages) NXP Semiconductors – CMOS single-chip 8-bit microcontroller

Philips Semiconductors
CMOS single-chip 8-bit microcontrollers
Product specification
80C528/83C528
DESCRIPTION
The 8XC528 single-chip 8-bit microcontroller
is manufactured in an advanced CMOS
process and is a derivative of the 80C51
microcontroller family. The 8XC528 has the
same instruction set as the 80C51. Three
versions of the derivative exist:
• 83C528 — 32k bytes mask programmable
ROM
• 80C528 — ROMless version of the
83C528
• 87C528 — 32k bytes EPROM (described
in a separate data sheet)
This device provides architectural
enhancements that make it applicable in a
variety of applications in consumer, telecom
and general control systems, especially in
those systems which need large ROM and
RAM capacity on-chip.
The 8XC528 contains a 32k × 8 ROM
(83C528), a 512 × 8 RAM, four 8-bit I/O
ports, two 16-bit timer/event counters
(identical to the timers of the 80C51), a 16-bit
timer (identical to the timer 2 of the 80C52), a
watchdog timer with a separate oscillator, a
multi-source, two-priority-level, nested
interrupt structure, two serial interfaces
(UART and I²C-bus), and on-chip oscillator
and timing circuits.
In addition, the 8XC528 has two software
selectable modes of power reduction — idle
mode and power-down mode. The idle mode
freezes the CPU while allowing the RAM,
timers, serial port, and interrupt system to
continue functioning. The power-down mode
saves the RAM contents but freezes the
oscillator, causing all other chip functions to
be inoperative.
PIN CONFIGURATIONS
FEATURES
• 80C51 instruction set
– 32k × 8 ROM (83C528)
– ROMless (80C528)
– 512 × 8 RAM
– Memory addressing capability
64k ROM and 64k RAM
– Three 16-bit counter/timers
– On-chip watchdog timer with oscillator
– Full duplex UART
– I²C serial interface
– Four 8-bit I/O ports
• Power control modes:
– Idle mode
– Power-down mode
– Warm start from power-down
• CMOS and TTL compatible
• Extended temperature ranges
• ROM code protection
• 7-source and 7-vector interrupt structure
with 2 priority levels
• Up to 3 external interrupt request inputs
• Two programmable power reduction modes
(Idle and Power-down)
• Termination of Idle mode by any interrupt,
external or WDT (watchdog) reset
• XTAL frequency range: 1.2 MHz to 16 MHz
T2/P1.0 ¹
T2EX/P1.1 2
40 V_DD
39 P0.0/AD0
P1.2 3
38 P0.1/AD1
P1.3 4
37 P0.2/AD2
P1.4 5
36 P0.3/AD3
P1.5 6
35 P0.4/AD4
SCL/P1.6 7
34 P0.5/AD5
SDA/P1.7 8
33 P0.6/AD6
RST 9
32 P0.7/AD7
RxD/P3.0 10
TxD/P3.1 11
DUAL
IN-LINE
PACKAGE
31 EA
30 ALE
INT0/P3.2 12
29 PSEN
INT1/P3.3 13
28 P2.7/A15
T0/P3.4 14
27 P2.6/A14
T1/P3.5 15
26 P2.5/A13
WR/P3.6 16
25 P2.4/A12
RD/P3.7 17
24 P2.3/A11
XTAL2 18
23 P2.2/A10
XTAL1 19
22 P2.1/A9
V_SS 20
21 P2.0/A8
* DO NOT CONNECT
T2/P1.0 ¹
T2EX/P1.1 2
42 V_DD
41 P0.0/AD0
P1.2 3
40 P0.1/AD1
P1.3 4
39 P0.2/AD2
P1.4 5
38 P0.3/AD3
P1.5 6
37 P0.4/AD4
SCL/P1.6 7
36 P0.5/AD5
SDA/P1.7 8
35 P0.6/AD6
RST 9
34 P0.7/AD7
RxD/P3.0 10
NC* 11
TxD/P3.1 12
SHRINK
DUAL
IN-LINE
PACKAGE
33 EA
32 _NC*
31 ALE
INT0/P3.2 13
30 PSEN
INT1/P3.3 14
29 P2.7/A15
T0/P3.4 15
28 P2.6/A14
T1/P3.5 16
27 P2.5/A13
WR/P3.6 17
26 P2.4/A12
RD/P3.7 18
25 P2.3/A11
XTAL2 19
24 P2.2/A10
XTAL1 20
23 P2.1/A9
V_SS 21
22 P2.0/A8
6
1
40
7
39
LEADED
CHIP
CARRIER
17
29
18
28
44
34
1
33
QUAD
FLAT
PACK
11
23
12
22
1995 Feb 02
2