80C528 Datasheet, PDF (13/26 Pages) NXP Semiconductors – CMOS single-chip 8-bit microcontroller

Philips Semiconductors
CMOS single-chip 8-bit microcontrollers
Product specification
80C528/83C528
DC ELECTRICAL CHARACTERISTICS (Continued)
T_amb = 0°C to +70°C (V_DD = 5V ±20%), –40°C to +85°C (V_DD = 5V ±20%), or –40°C to +125°C (V_DD = 5V ±10%), V_SS=0V
TEST
LIMITS
SYMBOL
PARAMETER
PART TYPE
CONDITIONS
MIN
MAX
UNIT
I_IL1
Input leakage current, port 0, EA
0.45<Vi<V_DD
±10
µA
I_IL2
Input leakage current, P1.6/SCL, P1.7/SDA
I_DD
Power supply current:
Active mode
Idle mode
Power down mode
Power down mode
0V<Vi<6.0V
0V<V_DD<6.0V
See notes 6, 7
–40°C to +125°C
±10
µA
µA
35
mA
6
mA
100
µA
150
µA
R_RST
C_IO
Internal reset pull-down resistor
Capacitance of I/O buffer
50
Freq.=1MHz
T_amb = 25°C
150
kΩ
10
pF
NOTES:
1. Capacitive loading on Port 0 and Port 2 may cause spurious noise pulses to be superimposed on the LOW level ouput voltage of ALE, Port
1 and Port 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make a 1-to-0
transition during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE line may exceed 0.8V. In such
cases it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input.
2. Capacitive loading on Port 0 and Port 2 may cause the HIGH level output voltage on ALE and PSEN to momentarily fall below the 0.9V_DD
specification when the address bits are stabilizing.
3. The input threshold voltage of P1.6 and P1.7 (SIO1) meets the I²C specification, so a voltage below 0.3V_DD will be recognized as a logic 0
while an input above 0.7V_DD will be recognized as a logic 1.
4. Under steady state (non-transient) conditions, I_OL must be externally limited as follows:
Maximum I_OL per port pin:
10mA
Maximum I_OL per 8–bit port: –
Port 0: 26mA
Ports 1, 2, & 3: 15mA
Maximum total I_OL for all output pins: 71mA
If I_OL exceeds the test condition, V_OL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed
test conditions.
5. Pins of ports 1, 2, and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
maximum value when V_IN is approximately 2V.
6. See Figures 9 through 12 for I_DD test conditions.
7. I_DDMAX at other frequencies can be derived from the figure below, where FREQ is the external oscillator frequency in MHz.
I_DDMAX is given in mA.
35
MAX ACTIVE MODE
30
25
20
TYP ACTIVE MODE
15
10
MAX IDLE MODE
5
TYP IDLE MODE
0
4
8
12
16
FREQ. AT XTAL1 (MHz)
VALID ONLY WITHIN FREQUENCY SPECIFICATIONS OF DEVICE UNDER TEST.
I_DD vs. FREQUENCY
1995 Feb 02
13